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preliminary user?s manual target cpu cores nu85ea nu85et ndu85etv14 memory controller NT85E500, ndt85e500v10, nt85e502 document no. a15019ej3v0um00 (3rd edition) date published september 2002 n cp(n) 1991 printed in japan 2000
preliminary user's manual a15019ej3v0um 2 [memo]
preliminary user's manual a15019ej3v0um 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
preliminary user's manual a15019ej3v0um 4 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? not all devices/types available in every country. please check with local nec representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12
preliminary user's manual a15019ej3v0um 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v?lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290
preliminary user's manual a15019ej3v0um 6 major revisions in this edition page description throughout addition of ndt85e500v10 (cb-12 family l type) p.18 addition of caution in 1.1.3 (2) (c) bus arbitration controller p.22 addition of busst in 1.2.1 list of pin functions p.29 addition of description in 1.2.2 (3) (k) dc3 to dc0 p.30 addition of figure 1-3 dcn pin timing p.30 addition of description in 1.2.2 (3) (l) csz7 to csz0 p.31 addition of 1.2.2 (3) (r) busst pp.32, 33 addition of description in 1.2.2 (4) nt85e502 connection pins pp.59, 60 addition of 1.3.7 (3) restriction related to page rom access p.64 addition of busst in figure 1-24 sram read timing (bus cycle period doubled) p.66 addition of description in 1.4 test function p.64 in previous edition deletion of 1.4.1 pin processing when in test mode p.94 addition of vpdv in 2.2.3 recommended connection of unused pins p.96 addition of caution 4 in 2.3.1 sdram configuration register n (scrn) pp.132, 133 addition of appendix c revision history the mark shows major revised points.
preliminary user's manual a15019ej3v0um 7 introduction target readers this manual is intended for users who wish to understand the functions of the memory controllers (NT85E500, ndt85e500v10, nt85e502) for the nu85ea, nu85et, and ndu85etv14 cpu cores for cbics and who design application systems using these cpu cores. memory controller target cpu core NT85E500, nt85e502 (cb-10 family vx type) nu85ea, nu85et ndt85e500v10 (cb-12 family l type) ndu85etv14 purpose this manual?s purpose is to help the user understand the functions of the NT85E500, ndt85e500v10, and nt85e502. organization this manual consists of the following. chapter 1 NT85E500 this chapter explains the NT85E500, which is the basic macro for controlling external memory. the NT85E500 is a memory controller for the nu85ea, nu85et, and ndu85etv14. the NT85E500 and ndt85e500v10 contain an on-chip sram, i/o controller, and page rom controller. chapter 2 nt85e502 this chapter explains the nt85e502, which is an sdram controller. how to use this manual this manual assumes that the reader has general knowledge of electrical engineering, logic circuits, microcontrollers, sram, page rom, and sdram. to gain a general understanding of the NT85E500, ndt85e500v10, and nt85e502 functions: read this manual according to the contents . to confirm details of a function, etc. when the name is known refer to appendix b index . to know the functions of the nu85ea in detail: refer to nu85e hardware user?s manual (a14874e). to know the functions of the nu85et and ndu85etv14 in detail: refer to nu85et hardware user?s manual (a15015e) .
preliminary user's manual a15019ej3v0um 8 in this manual, unless specified otherwise, the NT85E500 and nt85e502 are described as the representative memory controller. when using the ndt85e500v10, read ?ndt85e500v10? for the macro name of the memory controller (NT85E500). the nu85ea is described as the representative cpu core. when using the nu85et or ndu85etv14, read ?nu85et? or ?ndu85etv14? for the cpu core name. conventions data significance: higher digits on the left and lower digits on the right active low representation: xxxz (z is appended to pin or signal name) note: footnote for item marked with note in the text caution: information requiring particular attention remark: supplementary information numerical representation: binary ? xxxx or xxxxb decimal ? xxxx hexadecimal ? xxxxh prefix indicating the power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 data types: word ? 32 bits halfword ? 16 bits byte ? 8 bits related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? nu85e hardware user?s manual (a14874e) ? nu85et hardware user?s manual (a15015e) ? cb-10 family vx type nu85e, nu85et design manual (a15401e) ? cb-10 family vx type core library cpu core, peripheral design manual (a15133e) ? how to use sdram user?s manual (e0123n note ) ? synchronous dram user?s manual (e0124n note ) note this is a document published by elpida memory, inc. (http://www.elpida- memory.com/). the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
preliminary user's manual a15019ej3v0um 9 contents chapter 1 NT85E500 ............................................................................................................ ..................14 1.1 outline ................................................................................................................... .........................14 1.1.1 features................................................................................................................ .............................. 15 1.1.2 symbol diagram ......................................................................................................... ......................... 16 1.1.3 block diagram ........................................................................................................... .......................... 17 1.1.4 configuration example ................................................................................................... ..................... 19 1.1.5 functional differences between NT85E500 and nu85e500 .............................................................. 20 1.2 pin functions ............................................................................................................. ...................21 1.2.1 list of pin functions ................................................................................................... .......................... 21 1.2.2 explanation of pin functions............................................................................................ .................... 24 1.2.3 recommended connection of unused pins................................................................................... ...... 34 1.2.4 pin status .............................................................................................................. .............................. 35 1.3 bus cycle function.......................................................................................................... .............37 1.3.1 bus cycle type configuration registers 0 and 1 (bct0 and bct1)...................................................... 37 1.3.2 address setting wait control register (asc) ............................................................................. ........... 39 1.3.3 bus cycle control register (bcc)........................................................................................ ................. 40 1.3.4 data wait control registers 0 and 1 (dwc0 and dwc1) ..................................................................... 41 1.3.5 sram cycle .............................................................................................................. .......................... 43 1.3.6 page rom configuration register (prc)................................................................................... .......... 51 1.3.7 page rom cycle .......................................................................................................... ....................... 53 1.3.8 bus hold function ....................................................................................................... ......................... 61 1.3.9 bus cycle period control register (bcp) ................................................................................. ............. 63 1.3.10 stop function........................................................................................................... .......................... 65 1.4 test function............................................................................................................. ....................66 1.5 data flow ................................................................................................................. ......................67 1.5.1 data flow for byte access (8 bits)...................................................................................... .................. 68 1.5.2 data flow for halfword access (16 bits) ................................................................................. .............. 72 1.5.3 data flow for word access (32 bits)..................................................................................... ................ 76 chapter 2 nt85e502 ............................................................................................................ ..................82 2.1 outline ................................................................................................................... .........................82 2.1.1 features................................................................................................................ .............................. 83 2.1.2 symbol diagram .......................................................................................................... ........................ 84 2.1.3 block diagram ........................................................................................................... .......................... 85 2.1.4 configuration example ................................................................................................... ..................... 86 2.1.5 functional differences between nt85e502 and nu85e502 .............................................................. 88 2.2 pin functions............................................................................................................. ....................89 2.2.1 list of pin functions ................................................................................................... .......................... 89 2.2.2 explanation of pin functions............................................................................................ .................... 90 2.2.3 recommended connection of unused pins................................................................................... ...... 94
preliminary user's manual a15019ej3v0um 10 2.2.4 pin status .............................................................................................................. ..............................94 2.3 bus cycle function .......................................................................................................... .............95 2.3.1 sdram configuration register n (scrn)................................................................................... ..........96 2.3.2 sdram cycle ............................................................................................................. .......................103 2.3.3 sdram refresh control register n (rfsn)................................................................................. ........118 2.3.4 cbr refresh function..................................................................................................... ....................120 2.3.5 self-refresh function ................................................................................................... .......................122 2.3.6 notes on refresh function ............................................................................................... ...................124 2.4 test function ............................................................................................................. ..................126 2.4.1 pin processing when in test mode ........................................................................................ ............127 appendix a connection example ................................................................................................. 128 appendix b index .............................................................................................................. ...................130 appendix c revision history................................................................................................... .......132
preliminary user's manual a15019ej3v0um 11 list of figures (1/2) figure no. title page 1-1 sram and sdram connection example .......................................................................................... ...............14 1-2 application example ........................................................................................................ ..................................19 1-3 dcn pin timing ............................................................................................................. ....................................30 1-4 bus cycle type configuration registers 0 and 1 (bct0 and bct1) ............................................................. ...38 1-5 address setting wait control register (asc) ................................................................................ ...................39 1-6 bus cycle control register (bcc) ........................................................................................... .........................40 1-7 data wait control registers 0 and 1 (dwc0 and dwc1)........................................................................ .........41 1-8 sram connection example .................................................................................................... ..........................43 1-9 sram read timing ........................................................................................................... ................................45 1-10 sram write timing ......................................................................................................... ..................................46 1-11 sram read/write timing.................................................................................................... ..............................47 1-12 sram flyby cycle timing (sram i/o) .........................................................................................................49 1-13 sram flyby cycle timing (i/o sram) .........................................................................................................50 1-14 page rom configuration register (prc) ..................................................................................... ....................51 1-15 example of control using bits ma6 to ma3 .................................................................................. ....................52 1-16 page rom connection example (for 16-bit data bus) ......................................................................... ............53 1-17 page rom connection example (for 8-bit data bus) .......................................................................... .............54 1-18 page rom read timing ..................................................................................................... ..............................56 1-19 page rom flyby cycle timing (page rom i/o) ..........................................................................................58 1-20 memory map configuration example (when restriction applies)............................................................... ......59 1-21 memory map configuration example (when restriction does not apply)........................................................ 60 1-22 bus hold timing ........................................................................................................... .....................................62 1-23 bus cycle period control register (bcp) ................................................................................... ......................63 1-24 sram read timing (bus cycle period doubled)............................................................................... ...............64 1-25 NT85E500 operation at time of stop mode transition ........................................................................ ..........65 1-26 connection of NT85E500 to nu85ea in test mode............................................................................. .............66 1-27 byte access (little endian)............................................................................................... .................................68 1-28 byte access (big endian) ................................................................................................. ................................70 1-29 halfword access (little endian)........................................................................................... ..............................72 1-30 halfword access (big endian) ............................................................................................. .............................74 1-31 word access (little endian) .............................................................................................. ...............................76 1-32 word access (big endian) ................................................................................................. ...............................79 2-1 NT85E500 and nt85e502 connection example ................................................................................... ...........82 2-2 application example ........................................................................................................ ..................................86 2-3 connection example ......................................................................................................... ................................87 2-4 sdram configuration register n (scrn) ..................................................................................... ...................96 2-5 64 mb sdram connection example............................................................................................. ..................103 2-6 state transition of sdram access........................................................................................... ......................104 2-7 read/write data flow for sdram ............................................................................................. .....................105 2-8 sdram register write operation timing ...................................................................................... .................107 2-9 sdram single read cycle (32-bit data bus, word access) .................................................................... ....108 2-10 sdram single write cycle (32-bit data bus, word access) .................................................................. .......110
preliminary user's manual a15019ej3v0um 12 list of figures (2/2) figure no. title page 2-11 sdram continuous read cycle (32-bit data bus, word access, on-page) ................................................ 112 2-12 sdram continuous write cycle (32-bit data bus, word access, on-page) ................................................ 113 2-13 sdram sequential read cycle (16-bit data bus, word access, page change, cas latency = 2, bcw = 2)................................................ 114 2-14 sdram sequential read cycle (8-bit data bus, word access, page change, cas latency = 2, bcw = 2).................................................. 115 2-15 sdram sequential write cycle (16-bit data bus, word access, bank change, cas latency = 2, bcw = 1)................................................ 116 2-16 sdram sequential write cycle (8-bit data bus, word access, bank change, cas latency = 2, bcw = 1).................................................. 117 2-17 sdram refresh control register n (rfsn) .................................................................................. ................ 118 2-18 sdram cbr refresh timing .................................................................................................. ....................... 121 2-19 sdram self-refresh timing ................................................................................................. ......................... 123 2-20 refresh timing during dma line transfer................................................................................... .................. 125 2-21 connection of nt85e502 to nu85ea in test mode............................................................................. .......... 126 a-1 connection example of nu85ea, memcs and external memories (sram and sdram)............................. 129
preliminary user's manual a15019ej3v0um 13 list of tables table no. title page 1-1 vbbenz3 to vbbenz0 signals ................................................................................................. .......................24 1-2 vbctyp2 to vbctyp0 signals ................................................................................................. .......................25 1-3 vbseq2 to vbseq0 signals ................................................................................................... .........................25 1-4 pin status in each operating mode .......................................................................................... ........................35 1-5 list of control registers .................................................................................................. ..................................37 2-1 vbbenz3 to vbbenz0 signals ................................................................................................. .......................90 2-2 vbseq2 to vbseq0 signals ................................................................................................... .........................91 2-3 pin status in each operating mode .......................................................................................... ........................94 2-4 row address output ......................................................................................................... ................................98 2-5 column address output ...................................................................................................... ..............................98 2-6 examples of sdram refresh intervals........................................................................................ ...................119
preliminary user's manual a15019ej3v0um 14 chapter 1 NT85E500 1.1 outline the NT85E500, which is the basic macro for controlling external memory, contains an on-chip sram, i/o controller, and page rom controller. an external bus cycle can be started by connecting the NT85E500 to the nu85ea via the vsb. also, sdram can be controlled by connecting the sdram controller (nt85e502) to the NT85E500 (see figure 1- 1 ). figure 1-1. sram and sdram connection example note up to eight controllers can be connected. nu85ea NT85E500 asic v s b nt85e502 note sdram sram
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 15 1.1.1 features (1) sram-and-i/o controller the NT85E500 has one on-chip sram-and-i/o controller, which controls access to all csn areas (n = 7 to 0). its main features are as follows. ? sram can be accessed in at least 2 states. ? up to 7 programmable data wait states can be inserted by means of dwc0 and dwc1 register settings. ? up to 3 address setting wait states can be inserted by means of an asc register setting. ? the data wait can be controlled by waitz input. ? up to 3 idle states can be inserted after a read/write cycle by means of a bcc register setting. ? a dma flyby cycle note (sram i/o or i/o sram) can be started. note flyby transfer using sdram is not supported. (2) page rom controller the NT85E500 has one on-chip page rom controller, which controls access to all csn areas (n = 7 to 0). the basic bus cycles are the same as those of the sram-and-i/o controller, but this controller has a page access function. its main features are as follows. ? page rom can be accessed in at least 2 states. ? an on-page judgement function is available. ? the address to be compared can be changed by means of a prc register setting. ? for an on-page cycle, the active level (low level) for the rdz signal is maintained while the vbseq2 to vbseq0 signals indicate consecutive transfer (except the value ?vbseq2 to vbseq0 = 000?) until the vbseq2 to vbseq0 = 000 cycle is terminated. ? up to 7 programmable data wait states can be inserted during an off-page cycle by means of dwc0 and dwc1 register settings. ? up to 7 programmable data wait states can be inserted during an on-page cycle by means of a prc register setting. ? the data wait can be controlled by waitz input. ? a dma flyby cycle (page rom i/o) can be started. ? when there is a write cycle request for the csn area to which the page rom is connected, an sram write cycle is executed.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 16 1.1.2 symbol diagram vpdw (15:0) vbdi (31:0) vptclk in phtest in out phtdo (1:0) csz (7:0) astbz dstbz mpxcz rdcyz busst benz (3:0) refrqz selfref bcystz sdclk stprq stpak mce mpxen bcpen a (25:0) rdz wrz (3:0) iordz iowrz waitz hldrqz hldakz dc (3:0) di (31:0) vbdo (31:0) vpresz vbahld vblast vbseq (2:0) vbwrite vbstz vareq vpstb vpubenz vpwrite vaack vpdr (15:0) vbwait vpdv vpa (13:0) vba (25:0) vbbenz (3:0) vbctyp (2:0) vdcsz (7:0) vbclk out out out in out out in out in in out in out out out out in in out out in in in in out out out out in out in in in out in in in in in in in in in in in in in in in out out out out out out out out out out out out in in in in in in in out out out out out out in out out phtdin (1:0) in ct502i5 (1:0) ct501o0 (3:0) ct501o1 (3:0) ct501o7 (3:0) ct501i0 (2:0) ct501i3 (2:0) ct501i4 (2:0) ct501i6 (2:0) ct501i7 (2:0) ct501i5 (2:0) ct501i2 (2:0) ct501i1 (2:0) ct501o6 (3:0) ct501o5 (3:0) ct501o4 (3:0) ct501o3 (3:0) ct501o2 (3:0) ct502i0 (1:0) ct502o7 (1:0) bcp pisl ctl501 ct502i6 (1:0) ct502i4 (1:0) ct502i3 (1:0) ct502i2 (1:0) ct502i1 (1:0) rwc (7:0) ct502i7 (1:0) ct502o6 (1:0) ct502o5 (1:0) ct502o4 (1:0) ct502o3 (1:0) ct502o2 (1:0) ct502o1 (1:0) ct502o0 (1:0) out in do (31:0) out out out out out out out out out out out ctcso0 (4:0) ctlo (1:0) ctcsi7 (3:0) ctcsi6 (3:0) ctcsi5 (3:0) ctcsi4 (3:0) ctcsi3 (3:0) ctcsi2 (3:0) ctcsi1 (3:0) ctcsi0 (3:0) ctcso7 (4:0) ctcso6 (4:0) ctcso5 (4:0) ctcso4 (4:0) ctcso3 (4:0) ctcso2 (4:0) ctcso1 (4:0) mten out out in out out out out out in in in in in in in in
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 17 1.1.3 block diagram (1) internal block diagram npb signals vdcsz7 to vdcsz0 mce vbclk vsb signals test bus interface block ctcsin3 to ctcsin0, ctcson4 to ctcson0, ctlo1, ctlo0, mten, ct502in1, ct502in0, ct502on1, ct502on0 (n = 7 to 0) phtdin1, phtdin0 phtdo1, phtdo0 phtest csz7 to csz0 a25 to a0 do31 to do0 rdz wrz3 to wrz0 iordz iowrz dc3 to dc0 bcystz waitz refrqz hldrqz hldakz selfref sram/page rom controller vptclk bcpen benz3 to benz0 sram, i/o controller page rom controller stprq stpak di31 to di0 register block nt85e502 interface block bus arbitration controller
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 18 (2) internal units (a) register block the register block contains on-chip registers for controlling the bus cycle. these registers can be used to select external memory, set the number of idle or wait states, or set the number of consecutive reads of page rom. reading from or writing to the registers is done via the npb. (b) sram/page rom controller the sram/page rom controller controls read and write operations for sram, page rom, and external i/o. access to all csn areas can be controlled by this controller alone (n = 7 to 0). (c) bus arbitration controller this controller controls the bus mastership. when one of the following signals is received by the NT85E500, the controller activates the bus mastership request signal (vareq) to establish the NT85E500 as the bus master. ? stop mode request signal (stprq) from the nu85ea ? self-refresh request signal (selfref) ? external bus hold request signal (hldrqz) ? cbr refresh request from the nt85e502 when the stprq signal is received, an acknowledge signal for the stprq signal (stpak) is output to the nu85ea, and operation of the memc is stopped. also, if the stprq signal is received when the nt85e502 is connected, the stpak signal will be output after execution of a self-refresh cycle. the bus priority order is as follows. external bus hold request > refresh request > bus request from inside the nu85ea caution the NT85E500 does not output the vsb bus lock signal (vmlock). therefore, when designing a bus arbiter in a system in which multiple master devices exist on the vsb, design it to assign top priority to the NT85E500, so that bus mastership is not passed to another master device while the NT85E500 has the bus mastership. (d) nt85e502 interface block this is a block for interfacing with the nt85e502. it has a control signal for each csn area (n = 7 to 0). (e) test bus interface block this is a block for interfacing with signals used for testing the NT85E500. the NT85E500 can be tested by using the cpu core test mode.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 19 nu85ea NT85E500 sram, i/o page rom external bus master note asic v s b external bus 1.1.4 configuration example the NT85E500 starts bus cycles for external memory. the following figure shows an application example using the NT85E500. figure 1-2. application example note the NT85E500 has an external bus master arbitration function, which is controlled by the hldrqz and hldakz signals.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 20 1.1.5 functional differences between NT85E500 and nu85e500 item NT85E500 nu85e500 target cpu core nu85ea, nu85et, ndu85etv14 nb85e, nb85et vsb data bus (n = 31 to 0) vbdin (output), vbdon (input) vbdn (i/o) npb data bus (n = 15 to 0) vpdwn (input), vpdrn (output) vpdn (i/o) npb data output bus control pin vpdv (none) (none) vblock (i/o) (none) vbttyp1, vbttyp0 (i/o) (none) vbbstr (i/o) (none) vdselpz (i/o) vbbenz3 to vbbenz0 (input) vbbenz3 to vbbenz0 (i/o) vbwrite (input) vbwrite (i/o) vbstz (input) vbstz (i/o) vsb control pin vdcsz7 to vdcsz0 (input) vdcsz7 to vdcsz0 (i/o) data bus (n = 31 to 0) vbdon, vbdin vbdn i/o timing transfer response signal vbwait, vblast, vbahld vbdi31 to vbdi0, vbwait, vbahld, vblast, vpdr15 to vpdr0 low-level output pin status after reset, during idle do31 to do0 undefined high impedance
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 21 1.2 pin functions 1.2.1 list of pin functions (1/3) pin name i/o function vbclk input internal system clock i nput vdcsz7 to vdcsz0 input chip select input (for vsb) vba25 to vba0 input address input (for vsb) vbbenz3 to vbbenz0 input byte enable input (for vsb) vbctyp2 to vbctyp0 input bus cycle status i nput (for vsb) vbdo31 to vbdo0 input data input (for vsb) vbdi31 to vbdi0 output data output (for vsb) vbseq2 to vbseq0 input sequential status input (for vsb) vbwrite input read/write status input (for vsb) vbstz input transfer start input (for vsb) vareq output bus mastership request output (for vsb) vaack input bus mastership request acknowledge input (for vsb) vbwait output wait response output (for vsb) vbahld output address hold response output (for vsb) vblast output last response output (for vsb) vpstb input data strobe input (for npb) vpubenz input higher byte enable input (for npb) vpa13 to vpa0 input address input (for npb) vpwrite input write access strobe input (for npb) vpdw15 to vpdw0 input data input (for npb) vpdr15 to vpdr0 output data output (for npb) vpdv output data output (vpdr15 to vpdr0) control output (for npb) vpresz input reset input stprq input stop mode request input nu85ea connection pins stpak output acknowledge output for stprq input mce input bct register men bit reset value control input (n = 7 to 0) initialization pins bcpen input bcp register bcp bit reset value control input a25 to a0 output external memory address output di31 to di0 input external memory data input do31 to do0 output external memory data output external memory connection pins rdz output sram/page rom read strobe output
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 22 (2/3) pin name i/o function wrz3 to wrz0 output sram/page rom write strobe output iordz output external i/o read strobe output iowrz output external i/o write strobe output waitz input wait request input hldrqz input external bus hold request input hldakz output external bus hold request acknowledge output dc3 to dc0 output data bus control output csz7 to csz0 output chip select output benz3 to benz0 output byte enable output bcystz output bus cycle start status output refrqz output refresh status output selfref input self-refresh request input sdclk output sdram synchronization clock output external memory connection pins busst output bus strobe output ctcsi73 to ctcsi70 input control input from nt85e502 (for cs7 area) ctcsi63 to ctcsi60 input control input from nt85e502 (for cs6 area) ctcsi53 to ctcsi50 input control input from nt85e502 (for cs5 area) ctcsi43 to ctcsi40 input control input from nt85e502 (for cs4 area) ctcsi33 to ctcsi30 input control input from nt85e502 (for cs3 area) ctcsi23 to ctcsi20 input control input from nt85e502 (for cs2 area) ctcsi13 to ctcsi10 input control input from nt85e502 (for cs1 area) ctcsi03 to ctcsi00 input control input from nt85e502 (for cs0 area) ctcso74 to ctcso70 output control output to nt85e502 (for cs7 area) ctcso64 to ctcso60 output control output to nt85e502 (for cs6 area) ctcso54 to ctcso50 output control output to nt85e502 (for cs5 area) ctcso44 to ctcso40 output control output to nt85e502 (for cs4 area) ctcso34 to ctcso30 output control output to nt85e502 (for cs3 area) ctcso24 to ctcso20 output control output to nt85e502 (for cs2 area) ctcso14 to ctcso10 output control output to nt85e502 (for cs1 area) ctcso04 to ctcso00 output control output to nt85e502 (for cs0 area) ctlo1, ctlo0 output control output to nt85e502 mten output test mode enable output to nt85e502 ct502i71, ct502i70 input control input from nt85e502 (for cs7 area) ct502i61, ct502i60 input control input from nt85e502 (for cs6 area) ct502i51, ct502i50 input control input from nt85e502 (for cs5 area) ct502i41, ct502i40 input control input from nt85e502 (for cs4 area) ct502i31, ct502i30 input control input from nt85e502 (for cs3 area) ct502i21, ct502i20 input control input from nt85e502 (for cs2 area) nt85e502 connection pins ct502i11, ct502i10 input control input from nt85e502 (for cs1 area)
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 23 (3/3) pin name i/o function ct502i01, ct502i00 input control input from nt85e502 (for cs0 area) ct502o71, ct502o70 output control output to nt85e502 (for cs7 area) ct502o61, ct502o60 output control output to nt85e502 (for cs6 area) ct502o51, ct502o50 output control output to nt85e502 (for cs5 area) ct502o41, ct502o40 output control output to nt85e502 (for cs4 area) ct502o31, ct502o30 output control output to nt85e502 (for cs3 area) ct502o21, ct502o20 output control output to nt85e502 (for cs2 area) ct502o11, ct502o10 output control output to nt85e502 (for cs1 area) nt85e502 connection pins ct502o01, ct502o00 output control output to nt85e502 (for cs0 area) phtest input peripheral test mode status input phtdin1, phtdin0 input peripheral macro test input phtdo1, phtdo0 output peripheral macro test output test mode pins (connected to nu85ea) vptclk input test clock input mpxen input ct501i72 to ct501i70 input ct501i62 to ct501i60 input ct501i52 to ct501i50 input ct501i42 to ct501i40 input ct501i32 to ct501i30 input ct501i22 to ct501i20 input ct501i12 to ct501i10 input ct501i02 to ct501i00 input nec reserved pin (input low level) astbz output dstbz output mpxcz output rdcyz output busst output ct501o73 to ct501o70 output ct501o63 to ct501o60 output ct501o53 to ct501o50 output ct501o43 to ct501o40 output ct501o33 to ct501o30 output ct501o23 to ct501o20 output ct501o13 to ct501o10 output ct501o03 to ct501o00 output bcp output pisl output ctl501 output nec reserved pins rwc7 to rwc0 output nec reserved pin (leave open)
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 24 1.2.2 explanation of pin functions (1) nu85ea connection pins (a) vbclk (input) this is the external clock input pin for the internal system clock. a 50% duty stable clock is input from an external clock controller. (b) vdcsz7 to vdcsz0 (input) these are chip select pins and are connected to the vdcsz7 to vdcsz0 pins of the nu85ea. the nu85ea?s chip area select control registers (csc0, csc1) are used to set the vdcszn signal corresponding to the relevant bank of the data area and set multiple blocks (csn area) consisting of arbitrary bank combinations (n = 7 to 0). for further details, refer to the nu85e hardware user?s manual (a14874e). (c) vba25 to vba0 (input) these pins constitute an address input bus for the vsb and are connected to the vma25 to vma0 pins of the nu85ea. (d) vbbenz3 to vbbenz0 (input) these are low-level active pins that indicate the valid byte data out of the four data bus (vbdi31 to vbdi0, vbdo31 to vbdo0) parts and are connected to the vmbenz3 to vmbenz0 pins of the nu85ea. table 1-1. vbbenz3 to vbbenz0 signals active (low level) signal valid byte data vbbenz3 vbdi31 to vbdi24, vbdo31 to vbdo24 vbbenz2 vbdi23 to vbdi16, vbdo23 to vbdo16 vbbenz1 vbdi15 to vbdi8, vbdo15 to vbdo8 vbbenz0 vbdi7 to vbdi0, vbdo7 to vbdo0 (e) vbctyp2 to vbctyp0 (input) these are pins that input the current bus cycle status and are connected to the vmctyp2 to vmctyp0 pins of the nu85ea.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 25 table 1-2. vbctyp2 to vbctyp0 signals vbctyp2 vbctyp1 vbctyp0 bus cycle status 0 0 0 opcode fetch 0 0 1 data access 0 1 0 misalign access 0 1 1 read modify write access 1 0 0 opcode fetch of jump address due to branch instruction 1 1 0 dma 2-cycle transfer 1 1 1 dma flyby transfer 1 0 1 (reserved for future function expansion) remark 0: low-level input 1: high-level input (f) vbdo31 to vbdo0 (input) these pins constitute a data input bus for macro connected to vsb and are connected to the vbdo31 to vbdo0 pins of the nu85ea. (g) vbdi31 to vbdi0 (output) these pins constitute a data output bus for macro connected to vsb and are connected to the vbdi31 to vbdi0 pins of the nu85ea. (h) vbseq2 to vbseq0 (input) these are pins that input the sequential status indicating the transfer size during burst transfer and are connected to the vmseq2 to vmseq0 pins of the nu85ea. these pins indicate ?burst transfer length? at the start of burst transfer, ?continuous? during burst transfer, and ?single transfer? at the end of burst transfer. table 1-3. vbseq2 to vbseq0 signals vbseq2 vbseq1 vbseq0 sequential status 0 0 0 single transfer 0 0 1 continuous (indicates that the next transfer address is related to the current transfer address) note 0 1 0 continuous 4 times (burst transfer length: 4) 0 1 1 continuous 8 times (burst transfer length: 8) 1 0 0 continuous 16 times (burst transfer length: 16) 1 0 1 continuous 32 times (burst transfer length: 32) 1 1 0 continuous 64 times (burst transfer length: 64) 1 1 1 continuous 128 times (burst transfer length: 128) note this is output during continuous 2 times, or continuous 4, 8, 16, 32, 64, or 128 times transfer. remark 0: low-level input 1: high-level input
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 26 (i) vbwrite (input) this is an input pin that indicates the transfer direction and is connected to the vmwrite pin of the nu85ea. it inputs a high level during write. (j) vbstz (input) this is an input pin that indicates the start of transfer and is connected to the vmstz pin of the nu85ea. (k) vareq (output) this is the pin that outputs the bus mastership request signal and is connected to the vareq pin of the nu85ea. (l) vaack (input) this is an input pin that indicates the reception of the bus mastership request signal (vareq) and is connected to the vaack pin of the nu85ea. (m) vbwait (output) this is the wait response pin and is connected to the vmwait pin of the nu85ea. this signal is output to the bus master to request additional bus cycles because the data output preparations have not completed. when this signal becomes high level, the bus cycle changes to the wait status. (n) vbahld (output) this is the address hold response pin and is connected to the vmahld pin of the nu85ea. this signal is output to the bus master to request additional bus cycles when the data output preparations have completed. when this signal and the vbwait signal become high level, the bus cycle goes into the address hold status. since, in the address hold status, addresses do not change even during the data read and write cycles, there is no need to latch addresses and the circuit can thus be kept simple. when the number of idle states is set to 1 or more (bcn1 and bcn0 bits of bcc register = 01b or more), the NT85E500 activates the vbahld signal during the idle state at the end of the read cycle of an sram or page rom. (o) vblast (output) this is the last response pin and is connected to the vmlast pin of the nu85ea. this pin is used when the bus decoder requires a decode cycle. in the case of a system where several slave devices are connected externally and a bus decoder has been added to select slaves, decoding for bus slave selection is normally performed during non- sequential transfer. thus even when attempts to change a slave device are made during sequential transfer such as burst transfer, the decode cycle for slave selection cannot be issued. in such a case, the slave device outputs a last response notifying the fact that the slave selection signal has changed to the bus master. when there is a last response from the slave device, the bus master makes the next bus cycle non-sequential transfer to enable decode cycle issuance. the NT85E500 cannot activate the vblast signal.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 27 (p) vpstb (input) this is the data strobe input pin for the vpdw15 to vpdw0 signals and is connected to the vpstb pin of the nu85ea. (q) vpubenz (input) this is the higher byte enable input pin and is connected to the vpubenz pin of the nu85ea. it inputs a low level during a halfword data access or a byte data access to an odd address. it inputs a high level during a byte access to an even address. (r) vpa13 to vpa0 (input) these are address input pins for npb and are connected to the vpa13 to vpa0 pins of the nu85ea. they specify the lower 14 bits. (s) vpwrite (input) this is the write access strobe input pin for the vpdo15 to vpdo0 signals output from the nu85ea and is connected to the vpwrite pin of the nu85ea. it inputs a high level during write. (t) vpdw15 to vpdw0 (input) these pins constitute a bus for data input from the nu85ea and are connected to the vpdo15 to vpdo0 pins of the nu85ea. (u) vpdr15 to vpdr0 (output) these pins constitute a bus for data output to the nu85ea and are connected to the vpdi15 to vpdi0 pins of the nu85ea. (v) vpdv (output) this is the data output (vpdr15 to vpdr0) control pin. it outputs a high level during read. to configure a bidirectional data bus, connect this pin to the 3-state buffer enable pin connected to the data bus for data output control. this pin is not used when connecting with the nu85ea, therefore leave this pin open. (w) vpresz (input) this is the input pin for a system reset output from the nu85ea and is connected to the vpresz pin of the nu85ea. (x) stprq (input) this is the input pin for a hardware/software stop mode request from the nu85ea and is connected to the stprq pin of the nu85ea. (y) stpak (output) this is the output pin from which the acknowledge signal is sent to the nu85ea upon receipt of the stprq signal and is connected to the stpak pin of the nu85ea.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 28 (2) initialization pins (a) mce (input) this is a pin for specifying whether memc operation is enabled when a reset occurs. the reset value of the men bit of the bct0 or bct1 register is as follows according to the level input to this pin (n = 7 to 0). make sure that the level of this pin does not change before and after reset. ? low level: 0 (memc operation is disabled) ? high level: 1 (memc operation is enabled) (b) bcpen (input) this is a pin for specifying the length of the bus cycle period when a reset occurs. the reset value of the bcp bit of the bcp register is as follows according to the level input to this pin. make sure that the level of this pin does not change before and after reset. ? low level: 0 (normal) ? high level: 1 (double) (3) external memory connection pins (a) a25 to a0 (output) these pins constitute the external memory address bus. when the nt85e502 is active, all of the pins a25 to a0 output a low-level signal. (b) di31 to di0 (input) these pins constitute the data input bus for external memory. (c) do31 to do0 (output) these pins constitute the data output bus for external memory. (d) rdz (output) this is the read strobe output pin for making sram or page rom active. (e) wrz3 to wrz0 (output) these are the write strobe output pins for making sram or external i/o active. wrz3 ? for do31 to do24 wrz2 ? for do23 to do16 wrz1 ? for do15 to do8 wrz0 ? for do7 to do0 (f) iordz (output) this is the read strobe output pin for making external i/o active during a dma flyby cycle. (g) iowrz (output) this is the write strobe output pin for making external i/o active during a dma flyby cycle.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 29 (h) waitz (input) this is the pin to which a wait request is input from external memory. (i) hldrqz (input) this is the pin to which a bus hold request is input from an external source. an active level must be retained during a bus hold. (j) hldakz (output) this is the pin from which a bus hold acknowledge is output to an external source. it indicates that a bus hold is permitted. (k) dc3 to dc0 (output) these are the output pins for controlling the data bus i/o buffer direction. they output a high level when a read is performed and a low level when a write is performed. they output a high level during a dma flyby transfer. dc3 ? for di31 to di24, do31 to do24 dc2 ? for di23 to di16, do23 to do16 dc1 ? for di15 to di8, do15 to do8 dc0 ? for di7 to di0, do7 to do0 the dcn pin retains a low level for a write cycle and a high level for a read cycle during the ti cycle (n = 3 to 0). this pin becomes high level at the rising edge of the first vbclk in the read cycle and low level at the falling edge of the first vbclk in the write cycle (unaffected by the ta state and ti state). this pin outputs a low level for the consecutive write cycle of sram (see figure 1-3 (c) ).
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 30 figure 1-3. dcn pin timing (l) csz7 to csz0 (output) these are the chip select output pins. the values input to the vdcsz7 to vdcsz0 pins are output from these pins. however, when the nt85e502 is connected and executes a register write cycle or refresh cycle, the values input to the ct502i71 to ct502i01 pins are output from these pins. (a) write cycle read cycle (ta = 0, tw = 1) (b) write cycle read cycle (ta = 1, tw = 0) (c) consecutive write cycle of sram remark n = 3 to 0 wrzn (output) dcn (output) ta t1 tw t2 ti vbclk (input) ta t1 tw t2 ti write cycle write cycle vbstz (input) wrzn (output) rdz (output) t1 tw t2 ti t1 vbclk (input) tw t2 ti write cycle read cycle dcn (output) vbstz (input) wrzn (output) rdz (output) dcn (output) ta t1 t2 ti ta vbclk (input) t1 t2 ti write cycle read cycle
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 31 csz7 ... for cs7 area csz6 ... for cs6 area csz5 ... for cs5 area csz4 ... for cs4 area csz3 ... for cs3 area csz2 ... for cs2 area csz1 ... for cs1 area csz0 ... for cs0 area (m) benz3 to benz0 (output) these are the byte enable output pins. the values input to the vbbenz3 to vbbenz0 pins are output from these pins. (n) bcystz (output) this is the pin for indicating the bus cycle start status. (o) refrqz (output) this is the pin for indicating the execution status of the refresh cycle to sdram. it is used when an nt85e502 is connected. this pin outputs a low level when a refresh cycle is executed and a high level when a refresh cycle is not executed. if this pin outputs a low level during a bus hold, it indicates that a refresh request has been generated for the external bus master. (p) selfref (input) this is the self-refresh request input pin. it is used when an nt85e502 is connected. the input level to this pin indicates whether or not there is a self-refresh request. ? low level: there is no self-refresh request. ? high level: there is a self-refresh request. (q) sdclk (output) this is the synchronization clock output pin for external sdram. it is used when an nt85e502 is connected. (r) busst (output) this is the bus strobe output pin (1/2 frequency of vbclk). it rises at the td cycle and falls at the t1, t2, ta, tw, or ti cycle.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 32 (4) nt85e502 connection pins (a) ctcsin3 (n = 7 to 0) (input) this is the status signal input pin indicating that a refresh cycle is under execution. it is input from the nt85e502 for each csn area (n = 7 to 0). (b) ctcsin2 (n = 7 to 0) (input) this is the input pin indicating the end of self-refresh. it is input from the nt85e502 for each csn area (n = 7 to 0). (c) ctcsin1 (n = 7 to 0) (input) this is the refresh request signal input pin. it is input from the nt85e502 for each csn area (n = 7 to 0). (d) ctcsin0 (n = 7 to 0) (input) this is the test input pin. it is input from the nt85e502 for each csn area (n = 7 to 0). (e) ctcson4 (n = 7 to 0) (output) this is the bcn1 bit output pin of the bcc register of the NT85E500. it is output to the nt85e502 for each csn area (n = 7 to 0). (f) ctcson3 (n = 7 to 0) (output) this is the bcn0 bit output pin of the bcc register of the NT85E500. it is output to the nt85e502 for each csn area (n = 7 to 0). (g) ctcson2 (n = 7 to 0) (output) this is the refresh enable signal output pin. it is output to the nt85e502 for each csn area (n = 7 to 0). (h) ctcson1 (n = 7 to 0) (output) this is the btn0 bit output pin of the bct1 and bct0 registers of the NT85E500. it is output to the nt85e502 for each csn area (n = 7 to 0). when this pin becomes low level, the refresh counter of the nt85e502 is initialized asynchronously. an sdram cycle is not generated during low level. (i) ctcson0 (n = 7 to 0) (output) this is the men bit output pin of the bct1 and bct0 registers of the NT85E500. it is output to the nt85e502 for each csn area (n = 7 to 0). when this pin becomes low level, the nt85e502 state is initialized asynchronously. an sdram cycle is not generated during low level. (j) ctlo1 and ctlo0 (output) these are pins for controlling output to the nt85e502. (k) mten (output) this is the output pin for specifying whether test mode is enabled for the nt85e502. (l) ct502in1 (n = 7 to 0) (input) this is the csn input pin from the nt85e502 when a refresh is generated (n = 7 to 0). the cszn signal of the NT85E500 selects whether csn from vdcsz or csn from the nt85e502 is input with this signal.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 33 (m) ct502in0 (n = 7 to 0) (input) this is the input pin indicating the status of the power-on sequence. it is input from the nt85e502 for each csn area (n = 7 to 0). this pin outputs a high level during sdram power-on sequence execution after the scrn register is written. (n) ct502on1 (n = 7 to 0) (output) this is the output pin for selecting the scrn register. it is output to the nt85e502 for each csn area (n = 7 to 0). a write operation is performed to the internal registers of the nt85e502 using the anded signal of this signal and the vpstb signal. (o) ct502on0 (n = 7 to 0) (output) this is the output pin for selecting the rfsn register. it is output to the nt85e502 for each csn area (n = 7 to 0). a write operation is performed to the internal registers of the nt85e502 using the anded signal of this signal and the vpstb signal. (5) test mode pins (a) phtest (input) this is the status input pin, which indicates the test mode status of the memc. it is connected to the phtest pin of the nu85ea. (b) phtdin1 and phtdin0 (input) these are the test input pins. (c) phtdo1 and phtdo0 (output) these are the test output pins. (d) vptclk (input) this is the test clock input pin. (6) nec reserved pins (a) mpxen, ct501in2 to ct501in0 (n = 7 to 0) (input) these are nec reserved pins. be sure to input a low level. (b) astbz, dstbz, mpxcz, rdcyz, ct501on3 to ct501on0 (n = 7 to 0), bcp, pisl, ctl501, and rwc7 to rwc0 (output) these are nec reserved pins. leave open.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 34 1.2.3 recommended connection of unused pins pin name i/o recommended connection method vbclk, vdcsz7 to vdcsz0,vba25 to vba0, vbbenz3 to vbbenz0,vbctyp2 to vbctyp0, vbdo31 to vbdo0, vbseq2 to vbseq0, vbwrite, vbstz, vaack, vpstb, vpubenz, vpa13 to vpa0, vpwrite, vpdw15 to vpdw0, vpresz, stprq input vbdi31 to vbdi0, vareq, vbwait, vbahld, vblast, vpdr15 to vpdr0, stpak output always connected nu85ea connection pins vpdv output leave open. mce input input high level. initialization pins bcpen input input low level. a25 to a0, do31 to do0, rdz, wrz3 to wrz0, iordz, iowrz, hldakz, dc3 to dc0, csz7 to csz0, benz3 to benz0, bcystz, refrqz, sdclk output leave open. di31 to di0 input input low level or high level. waitz, hldrqz input input high level. external memory connection pins selfref input input low level. ctcsin3 to ctcsin0, ct502in1, ct502in0 input input low level. nt85e502 connection pins (n = 7 to 0) ctcson4 to ctcson0, ctlo1, ctlo0, mten, ct502on1, ct502on0 output leave open. phtest, phtdin1, phtdin0, vptclk input test mode pins phtdo1, phtdo0 output ? mpxen, ct501in2 to ct501in0 input input low level. nec reserved pins (n = 7 to 0) astbz, dstbz, mpxcz, rdcyz, busst, ct501on3 to ct501on0, bcp, pisl, ctl501, rwc7 to rwc0 output leave open.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 35 1.2.4 pin status the following table shows the status in each operating mode of the pins that have output functions. table 1-4. pin status in each operating mode pin status pin name reset stop mode halt mode bus hold test mode vbdi31 to vbdi0 l l operating l operating vareq l h operating h operating vbwait l l operating l operating vbahld l l operating l operating vblast l l operating l operating vpdr15 to vpdr0 l l operating l operating vpdv l l operating l operating nu85ea connection pins stpak l h operating l operating a25 to a0 undefined retained operating l operating do31 to do0 undefined undefined operating l operating rdz h h operating h operating wrz3 to wrz0 h h operating h operating iordz h h operating h operating iowrz h h operating h operating hldakz h h operating l operating dc3 to dc0 h h operating h operating csz7 to csz0 h h operating h operating benz3 to benz0 h h operating h operating bcystz h h operating h operating refrqz h l operating h note 1 operating external memory connection pins sdclk operating same as vbclk operating operating operating ctcson4, ctcson3 h retained operating retained operating ctcson2 l l operating l operating ctcson1 l retained operating retained operating ctcson0 note 2 retained operating retained operating ctlo1 l h operating l operating ctlo0 l l operating l operating mten llllh nt85e502 connection pins (n = 7 to 0) ct502on1, ct502on0 l l operating l operating test mode pins phtdo1, phtdo0 l l l l operating notes 1. if there is a refresh request from the nt85e502 during a bus hold, the pin status becomes a low-level output. 2. the status varies as follows depending on the input level of the mce pin. when a high level is input to the mce pin: h when a low level is input to the mce pin: l
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 36 remark l: low-level output h: high-level output retained: retains the previous status
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 37 1.3 bus cycle function in the bus cycle function of the NT85E500, the operation settings are made using the operation mode setting pins and the following control registers, which are assigned to the peripheral i/o area of the nu85ea. table 1-5. list of control registers bit units for manipulation address register name symbol r/w 1 bit 8 bits 16 bits after reset fffff480h bus cycle type configuration register 0 bct0 r/w 8888h/ 0000h fffff482h bus cycle type configuration register 1 bct1 r/w 8888h/ 0000h fffff484h data wait control register 0 dwc0 r/w 7777h fffff486h data wait control register 1 dwc1 r/w 7777h fffff488h bus cycle control register bcc r/w ffffh fffff48ah address setting wait control register asc r/w ffffh fffff48ch bus cycle period control register bcp r/w ? 80h/ 00h fffff49ah page rom configuration register prc r/w 7000h remark the settings of the NT85E500 control registers shown above are invalid for the rom and ram connected to the nu85ea?s vfb (v850e fetch bus) and vdb (v850e data bus) respectively. 1.3.1 bus cycle type configuration registers 0 and 1 (bct0 and bct1) the NT85E500 can connect four types of external memory (when connecting sdram, the nt85e502 is necessary). the bct0 and bct1 registers specify the controller and set whether operation is enabled for each csn area (n = 7 to 0). the bct0 and bct1 registers can be read or written in 16-bit units.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 38 figure 1-4. bus cycle type configuration registers 0 and 1 (bct0 and bct1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bct0 me3 0 bt31bt30 me2 0 bt21bt20 me1 0 bt11bt10 me0 0 bt01 bt00 address fffff480h after reset note bct1 me7 0 bt71bt70 me6 0 bt61bt60 me5 0 bt51bt50 me4 0 bt41 bt40 address fffff482h after reset note bit position bit name description 15, 11, 7, 3 men enable/disable operation of the memc for each csn area. 0: operation disabled (no response to the nu85ea) 1: operation enabled set the type of external memory to be connected for each csn area. btn1 btn0 external memory type 0 0 sram, i/o 0 1 page rom 1 0 setting prohibited 1 1 sdram (when the nt85e502 is connected) 13, 12, 9, 8, 5, 4, 1, 0 btn1, btn0 note when a high level is input to the mce pin: 8888h when a low level is input to the mce pin: 0000h caution bits btn1 and btn0 of the bct0 and bct1 registers should be set immediately after reset, and their settings should not be subsequently changed (the men bit can be changed). remark n = 7 to 0
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 39 1.3.2 address setting wait control register (asc) the NT85E500 can insert address setting wait states at the beginning of an sram or page rom cycle. the number of address setting wait states to be inserted can be set for each csn area by using the asc register (n = 7 to 0). the asc register can be read or written in 16-bit units. remarks 1. the settings of this register are invalid during an sdram cycle. 2. the external wait function using the waitz input is invalid during an address setting wait period. figure 1-5. address setting wait control register (asc) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 asc ac7 1 ac7 0 ac6 1 ac6 0 ac5 1 ac5 0 ac4 1 ac4 0 ac3 1 ac3 0 ac2 1 ac2 0 ac1 1 ac1 0 ac0 1 ac0 0 address fffff48ah after reset ffffh bit position bit name description set the number of address setting wait states to be inserted before an sram or page rom cycle for each csn area. acn1 acn0 number of wait states 0 0 none 011 102 113 15 to 0 acn1, acn0 remark n = 7 to 0
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 40 1.3.3 bus cycle control register (bcc) the NT85E500 can insert idle states at the end of a read or write cycle of an sram or page rom, and at the end of a read cycle of an sdram. the number of idle states to be inserted can be set for each csn area by using the bcc register (n = 7 to 0). these idle states are used to guarantee the interval until the external data bus is released by memory. the next bus cycle is started after the idle state(s). the bcc register can be read or written in 16-bit units. figure 1-6. bus cycle control register (bcc) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcc bc7 1 bc7 0 bc6 1 bc6 0 bc5 1 bc5 0 bc4 1 bc4 0 bc3 1 bc3 0 bc2 1 bc2 0 bc1 1 bc1 0 bc0 1 bc0 0 address fffff488h after reset ffffh bit position bit name description set the number of idle states to be inserted after a memory read or write cycle for each csn area. bcn1 bcn0 number of idle states 0 0 none 011 102 113 15 to 0 bcn1, bcn0 remark n = 7 to 0
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 41 1.3.4 data wait control registers 0 and 1 (dwc0 and dwc1) the NT85E500 can insert programmable data wait states for each csn area (n = 7 to 0). the dwc0 and dwc1 registers control the data wait states when accessing sram, i/o, and page rom (off-page cycle). the dwc0 and dwc1 registers can be read or written in 16-bit units. figure 1-7. data wait control registers 0 and 1 (dwc0 and dwc1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dwc0 0 dw3 2 dw3 1 dw3 0 0 dw2 2 dw2 1 dw2 0 0 dw1 2 dw1 1 dw1 0 0 dw0 2 dw0 1 dw0 0 address fffff484h after reset 7777h dwc1 0 dw7 2 dw7 1 dw7 0 0 dw6 2 dw6 1 dw6 0 0 dw5 2 dw5 1 dw5 0 0 dw4 2 dw4 1 dw4 0 address fffff486h after reset 7777h bit position bit name description set the number of wait states when accessing sram, i/o or page rom for each csn area. dwn2 dwn1 dwn0 number of wait states 0000 0011 0102 0113 1004 1015 1106 1117 14 to 12, 10 to 8, 6 to 4, 2 to 0 dwn2 to dwn0 remark n = 7 to 0
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 42 (1) external wait function when the NT85E500 is connected to a low-speed device or i/o, or to an asynchronous system, wait states can be inserted in the bus cycle by using the external wait input pin (waitz). external wait states are inserted only for the data wait cycle. external waits are sampled at the rising edge of the vbclk signal. the waitz input is sampled at the rising edge of the vbclk signal between the t1 cycle (or tw cycle) and the next cycle, and waits are only inserted in the data wait cycle. (2) data wait control registers and external waits the logical sum (or) of the number of waits set by data wait control registers 0 and 1 (dwc0 and dwc1) and the number of external waits from the waitz input is inserted for the wait cycle. therefore, the number of wait cycles that are inserted is equal to the larger of these two numbers of waits. for example, when the programmable wait and the waitz input have the following timings, the bus cycle contains 3 waits. programmable waits waits from waitz input wait control waitz input waits from waitz input programmable wait wait control t1 tw tw tw t2 vbclk
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 43 1.3.5 sram cycle (1) connection example figure 1-8. sram connection example dc0 a18 to a2 di31 to di24 csz rdz wrz3 NT85E500 di23 to di16 wrz2 di15 to di8 wrz1 di7 to di0 wrz0 do31 to do24 do23 to do16 do7 to do0 do15 to do8 a16 to a0 cs wr rd i/o8 to i/o1 sram (128 kwords 8 bits) dc3 a16 to a0 cs wr rd i/o8 to i/o1 sram (128 kwords 8 bits) dc2 dc1 a16 to a0 cs wr rd i/o8 to i/o1 sram (128 kwords 8 bits) a16 to a0 cs wr rd i/o8 to i/o1 sram (128 kwords 8 bits) i/o buffer i/o buffer i/o buffer i/o buffer
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 44 (2) bus timing examples of the bus timing for an sram read or write are shown below. an sram bus cycle consists of the following states. ? t1 and t2 states: basic states for access by the NT85E500. ? t3 state: basic state that is added during a flyby transfer. ? ta state: address setting wait state that is inserted according to the asc register settings. ? ti state: idle state that is inserted according to the bcc register settings. ? tw1 state: wait state that is inserted according to the dwc0 and dwc1 register settings. ? tw2 state: wait state caused by waitz input. remarks 1. circles indicate sampling timing. 2. : unknown state (output) or any level (input). 3. for details of vsb signals (vbxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) .
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 45 figure 1-9. sram read timing t1 vbclk (input) t2 t1 tw1 t2 ti tw2 t2 ta t1 t1 tw1 t2 vba25 to vba0 (input) vbwrite (input) dc3 to dc0 (output) vbdo31 to vbdo0 (input) vbbenz3 to vbbenz0 (input) vbseq2 to vbseq0 (input) vbctyp2 to vbctyp0 (input) wrz3 to wrz0 (output) vdcsz7 to vdcsz0 (input) di31 to di0 (input) vbstz (input) a25 to a0 (output) rdz (output) waitz (input) between cpu core and memc between memc and sram csz7 to csz0 (output) vbdi31 to vbdi0 (output) do31 to do0 (output) vbwait (output) vbahld (output) vblast (output) l l
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 46 figure 1-10. sram write timing vba25 to vba0 (input) vbwrite (input) t1 vbclk (input) dc3 to dc0 (output) vbwait (output) vbahld (output) vblast (output) vbdo31 to vbdo0 (input) vbbenz3 to vbbenz0 (input) vbseq2 to vbseq0 (input) vbctyp2 to vbctyp0 (input) wrz3 to wrz0 (output) vdcsz7 to vdcsz0 (input) vbstz (input) a25 to a0 (output) rdz (output) t2 t1 tw1 t2 t1 t2 ta t1 t2 tw1 tw2 waitz (input) between memc and sram csz7 to csz0 (output) vbdi31 to vbdi0 (output) do31 to do0 (output) l l between cpu core and memc di31 to di0 (input) ti
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 47 figure 1-11. sram read/write timing vba25 to vba0 (input) vbwrite (input) t1 vbclk (input) dc3 to dc0 (output) vbwait (output) vbahld (output) vblast (output) vbdo31 to vbdo0 (input) vbbenz3 to vbbenz0 (input) vbseq2 to vbseq0 (input) vbctyp2 to vbctyp0 (input) wrz3 to wrz0 (output) vdcsz7 to vdcsz0 (input) vbstz (input) a25 to a0 (output) rdz (output) t2 t1 tw1 t2 t1 tw1 t2 t1 t2 t2 t1 read cycle write cycle read cycle waitz (input) csz7 to csz0 (output) vbdi31 to vbdi0 (output) di31 to di0 (input) do31 to do0 (output) between memc and sram between cpu core and memc
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 48 examples of dma flyby cycle timing are shown below. a dma flyby cycle transfers data between external memory and i/o on a request from the dma controller.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 49 figure 1-12. sram flyby cycle timing (sram i/o) vba25 to vba0 (input) vbwrite (input) t1 vbclk (input) waitz (input) vbwait (output) vbahld (output) vblast (output) vbdo31 to vbdo0 (input) vbbenz3 to vbbenz0 (input) vbseq2 to vbseq0 (input) vbctyp2 to vbctyp0 (input) iowrz (output) vdcsz7 to vdcsz0 (input) di31 to di0 (input) vbstz (input) a25 to a0 (output) rdz (output) t2 t3 t1 tw1 t2 t1 tw1 tw2 t2 t3 ti t3 ta t1 t2 t3 (1,1,1) csz7 to csz0 (output) dc3 to dc0 (output) (1,1,1) (1,1,1) (1,1,1) vbdi31 to vbdi0 (output) l do31 to do0 (output) l l between cpu core and memc between memc and sram
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 50 figure 1-13. sram flyby cycle timing (i/o sram) vba25 to vba0 (input) vbwrite (input) t1 vbclk (input) waitz (input) vbwait (output) vbahld (output) vblast (output) vbdo31 to vbdo0 (input) vbbenz3 to vbbenz0 (input) vbseq2 to vbseq0 (input) vbctyp2 to vbctyp0 (input) wrz3 to wrz0 (output) vdcsz7 to vdcsz0 (input) di31 to di0 (input) vbstz (input) a25 to a0 (output) iordz (output) t2 t3 t1 tw1 t2 tw1 tw2 t2 t3 t3 t1 ta t1 t2 t3 (1,1,1) l (1,1,1) csz7 to csz0 (output) dc3 to dc0 (output) (1,1,1) (1,1,1) vbdi31 to vbdi0 (output) do31 to do0 (output) l between cpu core and memc between memc and sram l
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 51 1.3.6 page rom configuration register (prc) when a page rom bus cycle occurs, the NT85E500 judges whether or not it is an on-page access by comparing the address immediately after the page rom cycle that occurred with the current address. the address comparison width and the number of wait states during an on-page cycle are set using this register. this register can be read or written in 16-bit units. caution the number of wait states during an off-page cycle is set using the dwc0 and dwc1 registers. figure 1-14. page rom configuration register (prc) (1/2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prc 0 prw 2 prw 1 prw 0 00000000ma6ma5ma4ma3 address fffff49ah after reset 7000h bit position bit name description set the number of data wait states during a page rom on-page read cycle. prw2 prw1 prw0 number of data wait states 0000 0011 0102 0113 1004 1015 1106 1117 14 to 12 prw2 to prw0 caution the value set in the dwc0 and dwc1 registers is used for the number of wait states during the first page rom read (off-page read). if this is followed by consecutive on-page address reading, the wait state number set by the prw2 to prw0 bits is used. it is therefore necessary to set a wait state number in the dwc0 and dwc1 registers that satisfies the off- page read access time of the connected page rom and a wait state number in the prw2 to prw0 bits that satisfies the on-page read access time.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 52 figure 1-14. page rom configuration register (prc) (2/2) bit position bit name description set the mask bits for comparing addresses. ma6 ma5 ma4 ma3 number of consecutive reads 0 0 0 0 32 bits 2, 16 bits 4, 8 bits 8 0 0 0 1 32 bits 4, 16 bits 8, 8 bits 16 0 0 1 1 32 bits 8, 16 bits 16, 8 bits 32 0 1 1 1 32 bits 16, 16 bits 32, 8 bits 64 1 1 1 1 32 bits 32, 16 bits 64, 8 bits 128 3 to 0 ma6 to ma3 caution the ma6 to ma3 bits do not set the desired number of continuous accesses; use them to set the number of times consecutive reading can be executed during on-page access of the connected page rom. an example of address mask control when four 1-mword 8-bit page roms are connected is shown below. figure 1-15. example of control using bits ma6 to ma3 note not used for a 32-bit data bus. a25 a21 a8 a6 a5 a4 a3 ma6 0 ma5 0 ma4 0 ma3 1 a25 a21 a8 a7 a6 a5 a4 a3 a2 a1 a0 a19 a6 a5 a4 a3 a2 a1 a0 comparison ? ? ? ? ? note off-page address on-page address internal address latch (preceding address) page rom address prc register output address a7
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 53 1.3.7 page rom cycle (1) connection example figure 1-16. page rom connection example (for 16-bit data bus) a21 to a2 csz di15 to di0 rdz page rom (1 mword 16 bits) a19 to a0 ce oe o15 to o0 NT85E500 di31 to di16 i/o buffer i/o buffer page rom (1 mword 16 bits) a19 to a0 ce oe o15 to o0 dc1 dc0 dc3 dc2
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 54 NT85E500 a22 to a2 csz di7 to di0 rdz page rom (2 mwords 8 bits) a20 to a0 o7 to o0 di15 to di8 di23 to di16 di31 to di24 ce oe i/o buffer page rom (2 mwords 8 bits) a20 to a0 o7 to o0 ce oe i/o buffer page rom (2 mwords 8 bits) a20 to a0 o7 to o0 ce oe page rom (2 mwords 8 bits) a20 to a0 o7 to o0 ce oe i/o buffer i/o buffer dc0 dc1 dc2 dc3 figure 1-17. page rom connection example (for 8-bit data bus)
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 55 (2) bus timing examples of the bus timing for a page rom read are shown below. a page rom bus cycle consists of the following states. ? t1 and t2 states: basic states for access by the NT85E500. ? t3 state: basic state that is added during a flyby transfer. ? ta state: address setting wait state that is inserted according to the asc register settings. this state is inserted regardless of on-page/off-page. ? ti state: idle state that is inserted according to the bcc register settings. this state is inserted regardless of on-page/off-page. ? to1 and to2 states: sequential transfer basic states at the time of a page rom read. ? tw1 state: wait state that is inserted according to the dwc0 and dwc1 register settings. ? tw2 state: wait state caused by the waitz input. ? tw3 state: data wait state inserted according to the prc register settings during a page rom on-page read cycle. remarks 1. circles indicate sampling timing. 2. : unknown state (output) or any level (input). 3. for details of vsb signals (vbxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) .
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 56 figure 1-18. page rom read timing (1/2) (input) vbwrite (input) t1 vbclk (input) waitz (input) vbwait (output) vbahld (output) vblast (output) (input) (input) (input) (input) (input) do31 to do0 (output) vbstz (input) a25 to a0 (output) rdz (output) t2 t1 tw1 tw1 tw1 to1 tw3 to2 to1 tw1 t2 tw3 to2 to1 tw3 to2 ta to1 tw2 (0,0,0) (0,0,0) (0,0,0) (0,0,0) (0,0,0) (0,0,0) on-page cycle off-page cycle (output) (output) di31 to di0 (input) l l between cpu core and memc between memc and page rom vba25 to vba0 vbctyp2 to vbctyp0 vbbenz3 to vbbenz0 vbseq2 to vbseq0 vbdo31 to vbdo0 csz7 to csz0 vbdi31 to vbdi0 vdcsz7 to vdcsz0 to2
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 57 figure 1-18. page rom read timing (2/2) remark this figure indicates the timing when the rdz signal is held active (low level) during an on-page cycle (only when the vbseq2 to vbseq0 signals indicate consecutive transfer). (input) vbwrite (input) t1 vbclk (input) waitz (input) vbwait (output) vbahld (output) vblast (output) (input) (input) (input) (input) (input) do31 to do0 (output) vbstz (input) a25 to a0 (output) rdz (output) t2 t1 tw1 t2 ti to1 to2 to1 tw3 t1 t2 to2 to1 tw3 tw2 to2 ta t1 t2 (0,0,0) (0,0,0) (0,1,0) (0,0,1) (0,0,1) (0,0,0) (0,0,0) off-page cycle on-page cycle off-page cycle (output) (output) di31 to di0 (input) l l between cpu core and memc between memc and page rom vba25 to vba0 vbctyp2 to vbctyp0 vbbenz3 to vbbenz0 vbseq2 to vbseq0 vbdo31 to vbdo0 csz7 to csz0 vbdi31 to vbdi0 vdcsz7 to vdcsz0
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 58 figure 1-19. page rom flyby cycle timing (page rom i/o) remark this figure indicates the timing when the rdz signal is held active (low level) during an on-page cycle (only when the vbseq2 to vbseq0 signals indicate consecutive transfer and the number of wait states is set to 0 by the asc and bcc registers). (input) vbwrite (input) t1 vbclk (input) waitz (input) vbwait (output) vbahld (output) vblast (output) (input) (input) (input) (input) do31 to do0 (output) vbstz (input) a25 to a0 (output) rdz (output) t2 t3 t1 t2 t3 t2 t3 t1 t2 ti t1 t3 t1 tw2 t2 t3 t1 t2 t3 iowrz (output) (1,1,1) (1,1,1) (1,1,1) (1,1,1) (1,1,1) (1,1,1) l (0,0,0) (0,0,0) (0,1,0) (0,0,1) (0,0,1) (0,0,0) (output) (output) di31 to di0 (input) l l vba25 to vba0 vbctyp2 to vbctyp0 csz7 to csz0 vbseq2 to vbseq0 vbdo31 to vbdo0 vbdi31 to vbdi0 vdcsz7 to vdcsz0 between cpu core and memc between memc and page rom off-page cycle on-page cycle
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 59 (3) restriction related to page rom access when multiple page roms are connected to multiple different csn areas in the system, the following restriction related to page rom access applies (n = 0 to 7). caution page rom has a page access function and includes memory that enables high-speed consecutive access on the page. (a) restriction if the page rom of another csn area is accessed consecutively immediately after a page rom is accessed, when the address at which the page rom was accessed earlier and the address at which the page rom was accessed immediately after are on the same page of the page rom, an on-page cycle is also generated for the page rom accessed immediately after because it is mistakenly assumed that the same page rom is accessed, even though a different csn area is accessed (n = 0 to 7). as a result, the data access time for the page rom accessed immediately after is insufficient, and the read operation cannot be performed correctly. for example, in the case of the memory map configuration example shown in figure 1-20, an on-page cycle is generated for 8000002h if 8000002h of the cs4 area is accessed immediately after 0000000h of the cs0 area is accessed. figure 1-20. memory map configuration example (when restriction applies) 0000000h area 1 area 0 area 2 page rom bffffffh area 3 256 mb 3ffffffh 4000000h 7ffffffh 8000000h c000000h 8000000h 81fffffh fffffffh cs4 area cs0 area page rom 0000000h 01fffffh (01fffffh) (0000000h) address indicated by a25 to a0 (01fffffh) (0000000h)
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 60 if any of the following conditions applies, the restriction operation does not occur. ? when rom with page mode is not used when only one rom with page mode is used when rom with page mode is used only for program area when data area is used in 64 mb mode when rom with multiple page modes is used in cs0, cs1, and cs2 areas only when rom with multiple page modes is used in cs5, cs6, and cs7 areas only when the address indicated by a25 to a0 does not overlap in rom with multiple page modes (b) countermeasure when using multiple page roms, allocate each page rom so that the address indicated by a25 to a0 does not overlap. for example, when allocating two 2 mb page roms to different csn areas, allocate one page rom to 0000000h to 01fffffh, and allocate the other page rom to f800000h to f9fffffh, to configure the memory map shown in figure 1-21 (n = 0 to 7). figure 1-21. memory map configuration example (when restriction does not apply) 0000000h area 1 area 0 area 2 page rom bffffffh area 3 256 mb 3ffffffh 4000000h 7ffffffh 8000000h c000000h f800000h f9fffffh fffffffh cs0 area page rom 0000000h 01fffffh (39fffffh) (3800000h) address indicated by a25 to a0 (01fffffh) (0000000h) cs7 area
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 61 1.3.8 bus hold function when the hldrqz signal becomes active, the NT85E500 shifts to the bus hold status. when the transition into the bus hold status is completed, the hldakz signal becomes active. the hldakz signal retains an active level during a bus hold. during a bus hold, the bus master of the vsb becomes the NT85E500. design the external memory connection pins on the user logic side so that signals do not conflict during a bus hold. for details of pin statuses during a bus hold, refer to table 1-4 pin status in each operating mode . when the hldrqz signal becomes inactive, the NT85E500 shifts to the normal status. (1) bus hold procedure <1> an external bus hold request signal (hldrqz) is input for the NT85E500 from an external bus master. <2> the NT85E500 outputs a vsb mastership request signal (vareq) for the nu85ea. <3> the current bus cycle ends. <4> an acknowledge signal for the vareq signal (vaack) is input to the NT85E500 from the nu85ea. <5> the NT85E500 returns an acknowledge signal for the hldrqz signal (hldakz) to external memory. (2) bus hold release procedure <1> the hldrqz signal becomes inactive. <2> the bus hold request is released externally and the hldakz signal becomes inactive. <3> after the refresh cycle ends if a refresh request has been generated, or immediately if there is no refresh request, the vareq signal to the nu85ea becomes inactive. <4> the vaack signal from the nu85ea becomes inactive and the bus hold status ends. <5> the nu85ea becomes the master and a vsb bus cycle begins. (3) bus hold timing an example of bus hold timing is shown below. remarks 1. circles indicate sampling timing. 2. : unknown state (output) or any level (input). 3. for details of vsb signals (vbxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) .
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 62 figure 1-22. bus hold timing (input) vbwrite (input) vbclk (input) rdz (output) vbwait (output) vbahld (output) vblast (output) (input) (input) (input) vbstz (input) a25 to a0 (output) bcystz (output) (input) bus hold status vareq (output) vaack (input) hldrqz (input) hldakz (output) csz7 to csz0 (output) (output) l vba25 to vba0 vdcsz7 to vdcsz0 vbbenz3 to vbbenz0 vbseq2 to vbseq0 vbdo31 to vbdo0 vbdi31 to vbdi0 di31 to di0 (input)
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 63 1.3.9 bus cycle period control register (bcp) the NT85E500 can double the bus cycle period when accessing sram or page rom. control of the bus cycle period is performed using the bcp register. when the bcp bit of the bcp register is set (to 1), a dummy state (td) is inserted before each state of the bus cycle. the bcp register can be read or written in 8-bit or 1-bit units. caution this register?s settings are only valid when accessing sram or page rom (invalid when accessing sdram). figure 1-23. bus cycle period control register (bcp) 76543210 bcpbcp0000000 address fffff48ch after reset note bit position bit name description 7 bcp sets the length of the bus cycle period. 0: normal 1: double note on high-level input to bcpen pin: 80h on low-level input to bcpen pin: 00h an example of the timing when the bus cycle period is doubled is shown below. remarks 1. circles indicate sampling timing. 2. : unknown state (output) or any level (input). 3. for details of vsb signals (vbxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) .
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 64 figure 1-24. sram read timing (bus cycle period doubled) (input) vbwrite (input) vbclk (input) waitz (input) vbwait (output) vbahld (output) vblast (output) (input) (input) do31 to do0 (output) a25 to a0 (output) rdz (output) t1 t2 t1 t2 ti tw1 t1 tw1 tw2 (output) bcystz (output) t2 (input) (output) td td td td td td td td td td td (output) di31 to di0 (input) l l vba25 to vba0 vbbenz3 to vbbenz0 vbseq2 to vbseq0 vbdo31 to vbdo0 vbdi31 to vbdi0 vdcsz7 to vdcsz0 wrz3 to wrz0 csz7 to csz0 between cpu core and memc between memc and sram busst (output) read cycle read cycle read cycle vbstz (input) (input)
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 65 1.3.10 stop function when the nu85ea undergoes a transition to stop mode, the NT85E500 operates according to the following sequence (see figure 1-25 ). <1> when a hardware stop or software stop is executed, a stop mode request signal (stprq) is input from the nu85ea to the NT85E500. <2> the NT85E500 outputs a vsb mastership request signal (vareq) for the nu85ea. <3> an acknowledge signal for the vareq signal (vaack) is input from the nu85ea to the NT85E500. <4> the NT85E500 returns an acknowledge signal for the stprq signal (stpak) to the nu85ea. the NT85E500 returns the stpak signal no less than two clocks after receiving the stprq signal. moreover, if an nt85e502 is connected to the NT85E500, the stpak signal becomes active after the sdram self-refresh cycle is executed. figure 1-25. NT85E500 operation at time of stop mode transition nu85ea NT85E500 vareq vaack <2> <3> vareq vaack stprq stpak <1> <4> stprq stpak
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 66 1.4 test function the NT85E500 can be tested using the nu85ea test mode. to test the NT85E500, connect it to the nu85ea as follows. figure 1-26. connection of NT85E500 to nu85ea in test mode process each pin in the test mode as follows. (1) test mode pins connect test mode pins to the nu85ea as shown in figure 1-26. (2) other pins make other pins the same as in normal mode (if they are unused, process them according to 1.2.3 recommended connection of unused pins ). refer to 1.2.4 pin status regarding the pin status. the di31 to di0, hldrqz, waitz, and selfref signals are ignored regardless of the values that are input. remark for details about test modes, refer to the nu85e hardware user?s manual (a14874e) . vsb nu85ea NT85E500 vpresz phtdo1 phtdin0 vptclk phtdo0 vpresz vptclk phtdin1 phtdin0 phtdo1 phtdo0 phtest tbi39 tbi0 ? ? tbo34 tbo0 ? test bunri ? vbclk vbclk phtest phtdin1
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 67 1.5 data flow the flow of data transfer to external memory differs according to the register settings, starting addresses, and data width. data flows are shown below for each condition.
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 68 1.5.1 data flow for byte access (8 bits) figure 1-27. byte access (little endian) (1/2) data transfer flow address to be accessed external data bus: 32 bits 4n 4n v 0 7 8 15 16 23 24 31 d 0 7 8 15 16 23 24 31 address b 0 7 4n + 1 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 4n + 2 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 4n + 3 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+3 remark b: byte data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 69 figure 1-27. byte access (little endian) (2/2) data transfer flow address to be accessed external data bus: 16 bits external data bus: 8 bits 2n 2n v 0 7 8 15 16 23 24 31 d 0 7 8 15 b 0 7 address 2n v 0 7 8 15 16 23 24 31 d 0 7 b 0 7 address 2n + 1 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 address 2n+1 2n+1 v 0 7 8 15 16 23 24 31 d 0 7 b 0 7 address remark b: byte data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 70 figure 1-28. byte access (big endian) (1/2) data transfer flow address to be accessed external data bus: 32 bits 4n v 0 7 8 15 16 23 24 31 d 0 7 8 15 16 23 24 31 address b 0 7 4n 4n + 1 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 4n + 2 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 4n + 3 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+3 remark b: byte data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 71 figure 1-28. byte access (big endian) (2/2) data transfer flow address to be accessed external data bus: 16 bits external data bus: 8 bits 2n v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 address 2n 2n v 0 7 8 15 16 23 24 31 d 0 7 b 0 7 address 2n + 1 2n+1 v 0 7 8 15 16 23 24 31 d 0 7 8 15 b 0 7 address 2n+1 v 0 7 8 15 16 23 24 31 d 0 7 b 0 7 address remark b: byte data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 72 1.5.2 data flow for halfword access (16 bits) figure 1-29. halfword access (little endian) (1/2) (a) external data bus: 32 bits data transfer flow address to be accessed first time second time 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 4n 8 15 ? 4n + 1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 8 15 4n + 2 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 8 15 4n+3 ? 4n + 3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+4 remark hw: halfword data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 73 figure 1-29. halfword access (little endian) (2/2) (b) external data bus: 16 bits data transfer flow address to be accessed first time second time 2n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 2n+1 2n 8 15 address ? 2n + 1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 2n+1 8 15 address v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 2n+2 8 15 address (c) external data bus: 8 bits data transfer flow address to be accessed first time second time 2n 2n v 0 7 8 15 16 23 24 31 d 0 7 hw 0 7 address 8 15 2n+1 v 0 7 8 15 16 23 24 31 d 0 7 hw 0 7 8 15 address 2n + 1 2n+1 v 0 7 8 15 16 23 24 31 d 0 7 hw 0 7 address 8 15 2n+2 v 0 7 8 15 16 23 24 31 d 0 7 hw 0 7 8 15 address remark hw: halfword data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 74 figure 1-30. halfword access (big endian) (1/2) (a) external data bus: 32 bits data transfer flow address to be accessed first time second time 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 8 15 4n ? 4n + 1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+2 4n + 2 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 4n+3 8 15 ? 4n + 3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+3 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+4 8 15 remark hw: halfword data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 75 figure 1-30. halfword access (big endian) (2/2) (b) external data bus: 16 bits data transfer flow address to be accessed first time second time 2n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 2n 2n+1 8 15 address ? 2n + 1 v hw d 0 7 8 15 16 23 24 31 0 7 0 7 8 15 2n+1 8 15 address v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 2n+2 8 15 address (c) external data bus: 8 bits data transfer flow address to be accessed first time second time 2n 2n v 0 7 8 15 16 23 24 31 d 0 7 hw 0 7 8 15 address 2n+1 v 0 7 8 15 16 23 24 31 d 0 7 hw 0 7 address 8 15 2n + 1 2n+1 v 0 7 8 15 16 23 24 31 d 0 7 hw 0 7 8 15 address 2n+2 v 0 7 8 15 16 23 24 31 d 0 7 hw 0 7 address 8 15 remark hw: halfword data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 76 1.5.3 data flow for word access (32 bits) figure 1-31. word access (little endian) (1/3) (a) external data bus: 32 bits data transfer flow address to be accessed first time second time third time 4n v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 8 15 4n+3 16 23 24 31 4n+1 4n ?? 4n + 1 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+1 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+3 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+4 16 23 24 31 4n + 2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+3 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+5 4n+4 ? 4n + 3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+5 4n+4 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+6 remark w: word data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 77 figure 1-31. word access (little endian) (2/3) (b) external data bus: 16 bits data transfer flow address to be accessed first time second time third time 4n v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+1 4n 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 4n+2 8 15 address 16 23 24 31 ? 4n + 1 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+1 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 8 15 address 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 8 15 address 16 23 24 31 4n+4 4n + 2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 4n+2 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+5 4n+4 8 15 address 16 23 24 31 ? 4n + 3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+5 8 15 address 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 8 15 address 16 23 24 31 4n+6 remark w: word data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 78 figure 1-31. word access (little endian) (3/3) (c) external data bus: 8 bits data transfer flow address to be accessed first time second time third time fourth time 4n 4n v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n + 1 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n + 2 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n + 3 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+6 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 remark w: word data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 79 figure 1-32. word access (big endian) (1/3) (a) external data bus: 32 bits data transfer flow address to be accessed first time second time third time 4n v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 8 15 4n 16 23 24 31 4n+2 4n+3 ?? 4n + 1 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+1 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+2 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+4 16 23 24 31 4n + 2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+2 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+5 4n+4 ? 4n + 3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+4 4n+5 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+6 remark w: word data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 80 figure 1-32. word access (big endian) (2/3) (b) external data bus: 16 bits data transfer flow address to be accessed first time second time third time 4n v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n 4n+1 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+2 4n+3 8 15 address 16 23 24 31 ? 4n + 1 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+1 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+2 8 15 address 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 8 15 address 16 23 24 31 4n+4 4n + 2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+2 4n+3 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+4 4n+5 8 15 address 16 23 24 31 ? 4n + 3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+4 8 15 address 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 8 15 address 16 23 24 31 4n+6 remark w: word data v: vsb d: external data bus n = 0, 1, 2, 3, ?
chapter 1 NT85E500 preliminary user's manual a15019ej3v0um 81 figure 1-32. word access (big endian) (3/3) (c) external data bus: 8 bits data transfer flow address to be accessed first time second time third time fourth time 4n 4n v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n + 1 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n + 2 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n + 3 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+6 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 remark w: word data v: vsb d: external data bus n = 0, 1, 2, 3, ?
preliminary user's manual a15019ej3v0um 82 chapter 2 nt85e502 2.1 outline the nt85e502 is a macro for controlling synchronous dram (sdram). an external sdram bus cycle can be started by connecting the nt85e502 to the nu85ea via the NT85E500 and the vsb. the nt85e502 is used connected to the NT85E500. up to eight nt85e502 controllers can be connected. figure 2-1. NT85E500 and nt85e502 connection example note up to eight controllers can be connected. remark the nt85e502 only supports 12 row addresses and 10 column addresses. therefore, only sdrams of 128 mb or less can be connected. the maximum cs area in 256 mb mode is the 64 mb area of cs1, cs3, cs4, and cs6. if assigning sdrams to all of this 64 mb area, it is necessary that this area supports 512 mb (64 mb) with a 128 mb (4 mwords 8 bits 4 banks) 4 configuration, and 32-bit bus access. nu85ea NT85E500 asic nt85e502 note sdram v s b
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 83 2.1.1 features ? only a single access can be started. ? a command for continuous access indicated by the vbseq2 to vbseq0 pins can be issued continuously after a one-clock interval, for example in the following cases. ? when the external data bus is 8 bits and 16-/32-bit data is being read/written when the external data bus is 16 bits and 32-bit data is being read/written when the instruction cache/data cache is being refilled ? cas latency = 2 and 3 are supported. ? an address multiplex function is available. ? the column address width can be changed by means of an scrn register setting. ? up to 3 wait states can be inserted by means of an scrn register setting. ? a register write operation can be executed for each write access to the scrn register. ? a cbr (cas before ras) refresh command can be issued. remark n = 7 to 0
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 84 2.1.2 symbol diagram out in out out out out out in in in in out in out in in out out out out in in in in in out in in a (25:0) di (31:0) sdrasz sdcasz sdwez cke dqm (3:0) vptclk in vpwrite vpresz ct502i (1:0) ct502o (1:0) vbwrite vbwait vbahld ctlo1 vblast vpdr (15:0) ctcsi (3:0) ctcso (4:0) vpstb ctlo0 vbdi (31:0) vdcsz vbbenz (3:0) vba (25:0) vbclk vbseq (2:0) mten in hldakz in vpdw (15:0) out vpdv
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 85 2.1.3 block diagram npb pins control signals to NT85E500 vbclk vsb pins ctcsi3 to ctcsi0 test bus interface block a25 to a0 di31 to di0 sdrasz sdcasz sdwez cke main controller vptclk control signals from NT85E500 register block dqm3 to dqm0 refresh controller
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 86 2.1.4 configuration example the nt85e502 starts bus cycles for external sdram. the following figure shows an application example using the nt85e502. figure 2-2. application example note the NT85E500 has an external bus master arbitration function, which is controlled by the hldrqz and hldakz signals. sram, i/o page rom external bus master note asic v s b sdram nu85ea NT85E500 external bus nt85e502
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 87 the following figure shows an example of the connections between the NT85E500 and nt85e502 controllers. in this example, the nt85e502 controllers are connected to the cs7 and cs3 areas. figure 2-3. connection example or ctcsi3 to ctcsi0 ctcso4 to ctcso0 ct502i1, ct502i0 ct502o1, ct502o0 a25 to a0 mten ctlo1 ctlo0 hldakz NT85E500 ctcsi33 to ctcsi30 ctcso34 to ctcso30 ct502i31, ct502i30 ct502o31, ct502o30 ctcsi73 to ctcsi70 ctcso74 to ctcso70 ct502i71, ct502i70 ct502o71, ct502o70 mten ctlo1 ctlo0 a25 to a0 hldakz ctcsi3 to ctcsi0 ctcso4 to ctcso0 ct502i1, ct502i0 ct502o1, ct502o0 a25 to a0 mten ctlo1 ctlo0 hldakz nt85e502 nt85e502
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 88 2.1.5 functional differences between nt85e502 and nu85e502 item nt85e502 nu85e502 target cpu core nu85ea, nu85et nb85e, nb85et vsb data bus (n = 31 to 0) vbdin vbdn npb data bus (n = 15 to 0) vpdwn (input), vpdrn (output) vpdn (i/o) npb data output bus control pin vpdv (none) data bus (n = 31 to 0) vbdin vbdn i/o timing transfer response signal vbwait, vblast, vbahld pin status after reset, during idle vbdi31 to vbdi0, vbwait, vbahld, vblast, vpd15 to vpd0 low-level output high impedance
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 89 2.2 pin functions 2.2.1 list of pin functions pin name i/o function vbclk input internal system clock i nput vba25 to vba0 input address input (for vsb) vbdi31 to vbdi0 output data output (for vsb) vdcsz input chip select input (for vsb) vbbenz3 to vbbenz0 input byte enable input (for vsb) vbseq2 to vbseq0 input sequential status input (for vsb) vbwrite input read/write status input (for vsb) vbwait output wait response output (for vsb) vbahld output address hold response output (for vsb) vblast output last response output (for vsb) vpdw15 to vpdw0 input data input (for npb) vpdr15 to vpdr0 output data output (for npb) vpdv output data output (vpdr15 to vpdr0) control output (for npb) vpstb input data strobe input (for npb) vpwrite input write access strobe input (for npb) nu85ea connection pins vpresz input reset input ctcsi3 to ctcsi0 output control output to NT85E500 ctcso4 to ctcso0 input control input from NT85E500 ct502i1, ct502i0 output control output to NT85E500 ct502o1, ct502o0 input control input from NT85E500 ctlo1, ctlo0 input control input from NT85E500 mten input test mode enable input from NT85E500 NT85E500 connection pins hldakz input bus hold status input from NT85E500 a25 to a0 output external memory address output di31 to di0 input external memory data input sdrasz output sdram row address strobe output sdcasz output sdram column address strobe output sdwez output sdram data write enable output cke output clock enable output external memory connection pins dqm3 to dqm0 output data mask output test mode pin vptclk input test clock input
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 90 2.2.2 explanation of pin functions (1) nu85ea connection pins (a) vbclk (input) this is the external clock input pin for the internal system clock. a 50% duty stable clock is input from an external clock controller. (b) vba25 to vba0 (input) these pins constitute an address input bus for the vsb and are connected to the vma25 to vma0 pins of the nu85ea. (c) vbdi31 to vbdi0 (output) these pins constitute a data output bus for the vsb and are connected to the vbdi31 to vbdi0 pins of the nu85ea. (d) vdcsz (input) this is the low-level active chip select input pin and is connected to the vdcszn pin of the nu85ea (n = 7 to 0). for further details, refer to the nu85e hardware user?s manual (a14874e). (e) vbbenz3 to vbbenz0 (input) these are low-level active input pins that indicate the valid byte data out of the four data bus (vbdi31 to vbdi0) parts and are connected to the vmbenz3 to vmbenz0 pins of the nu85ea. table 2-1. vbbenz3 to vbbenz0 signals active (low-level input) signal valid byte data vbbenz3 vbdi31 to vbdi24 vbbenz2 vbdi23 to vbdi16 vbbenz1 vbdi15 to vbdi8 vbbenz0 vbdi7 to vbdi0 (f) vbseq2 to vbseq0 (input) these are pins that input the sequential status indicating the transfer size during burst transfer and are connected to the vmseq2 to vmseq0 pins of the nu85ea. these pins indicate ?burst transfer length? at the start of burst transfer, ?continuous? during burst transfer, and ?single transfer? at the end of burst transfer.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 91 table 2-2. vbseq2 to vbseq0 signals vbseq2 vbseq1 vbseq0 sequential status 0 0 0 single transfer 0 0 1 continuous (indicates that the next transfer address is related to the current transfer address) note 0 1 0 continuous 4 times (burst transfer length: 4) 0 1 1 continuous 8 times (burst transfer length: 8) 1 0 0 continuous 16 times (burst transfer length: 16) 1 0 1 continuous 32 times (burst transfer length: 32) 1 1 0 continuous 64 times (burst transfer length: 64) 1 1 1 continuous 128 times (burst transfer length: 128) note this is output during continuous 2 times, or continuous 4, 8, 16, 32, 64, or 128 times transfer. remark 0: low-level input 1: high-level input (g) vbwrite (input) this is an input pin that indicates the data transfer direction (read/write status) and is connected to the vmwrite pin of the nu85ea. it inputs a high level during write access. (h) vbwait (output) this is the wait response pin and is connected to the vmwait pin of the nu85ea. this signal is output to the bus master to request additional bus cycles because the data output preparations have not completed. when this signal becomes high level, the bus cycle changes to the wait status. (i) vbahld (output) this is the address hold response pin and is connected to the vmahld pin of the nu85ea. this signal is output to the bus master to request additional bus cycles when the data output preparations have completed. when this signal and the vbwait signal become high level, the bus cycle goes into the address hold status. since, in the address hold status, addresses do not change even during the data read and write cycles, there is no need to latch addresses and the circuit can thus be kept simple. when the number of idle states is set to 1 or more (bcn1 and bcn0 bits of bcc register = 01b or more), the nt85e502 activates the vbahld signal during idle state at the end of a read cycle of an sdram. (j) vblast (output) this is the last response pin and is connected to the vmlast pin of the nu85ea. this pin is used when the bus decoder requires a decode cycle. in the case of a system where several slave devices are connected externally and a bus decoder has been added to select slaves, decoding for bus slave selection is normally performed during non- sequential transfer.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 92 thus even when attempts to change a slave device are made during sequential transfer such as burst transfer, the decode cycle for slave selection cannot be issued. in such a case, the slave device outputs a last response notifying the fact that the slave selection signal has changed to the bus master. when there is a last response from the slave device, the bus master makes the next bus cycle non-sequential transfer to enable decode cycle issuance. the nt85e502 cannot activate the vblast signal. (k) vpdw15 to vpdw0 (input) these pins constitute a data input bus for npb and are connected to the vpdo15 to vpdo0 pins of the nu85ea. (l) vpdr15 to vpdr0 (output) these pins constitute a data output bus for npb and are connected to the vpdi15 to vpdi0 pins of the nu85ea. (m) vpdv (output) this is the data output (vpdr15 to vpdr0) control signal output pin. it outputs a high level during read. to configure a bidirectional data bus, connect this pin to the 3-state buffer enable pin connected to the data bus for data output control. this pin is not used when connecting with the nu85ea, therefore leave this pin open. (n) vpstb (input) this is the data strobe output pin for npb. (o) vpwrite (input) this is the write access strobe input pin for the vpdw15 to vpdw0 signals. it inputs a high level during write. (p) vpresz (input) this is the input pin for a system reset output from the nu85ea. (2) NT85E500 connection pins (a) ctcsi3 to ctcsi0 (output) these are pins for controlling output to the NT85E500. (b) ctcso4 to ctcso0 (input) these are pins for controlling input from the NT85E500. (c) ct502i1 and ct502i0 (output) these are pins for controlling output to the NT85E500. (d) ct502o1 and ct502o0 (input) these are pins for controlling input from the NT85E500. (e) ctlo1 and ctlo0 (input) these are pins for controlling input from the NT85E500.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 93 (f) mten (input) this is the pin to which the test mode enable is input from the NT85E500. (g) hldakz (input) this is the pin to which the bus hold status is input from the NT85E500. this is used only when the external bus master accesses sdram during a bus hold. input a high level when not being used. cautions 1. when accessing the sdram using the external bus master during a bus hold, be sure to perform access after issuing the precharge command. 2. do not rewrite sdram configuration register n (scrn) (n = 7 to 0) using the external bus master during a bus hold. remark after releasing a bus hold, when the nt85e502 regains bus mastership and accesses sdram, access starts from all bank precharge. (3) external memory connection pins (a) a25 to a0 (output) these pins constitute the external sdram address bus. when the vdcsz signal is inactive, all of the pins a25 to a0 output a low-level signal. (b) di31 to di0 (input) these pins constitute the external sdram data bus. (c) sdrasz (output) this is the row address strobe output pin for external sdram. (d) sdcasz (output) this is the column address strobe output pin for external sdram. (e) sdwez (output) this is the data write enable output pin for external sdram. (f) cke (output) this is the clock enable output pin for external sdram. this pin outputs an inactive (low level) during a self-refresh cycle. (g) dqm3 to dqm0 (output) these are the data mask output pins for external sdram. during a write cycle, they output the same values as the vmbenz3 to vmbenz0 signals of the nu85ea when a write command is performed. during a read cycle, the dqm3 to dqm0 pins all output a low level after a read command is performed. (4) test mode pin (a) vptclk (input) this is a test clock input pin.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 94 2.2.3 recommended connection of unused pins pin name i/o recommended connection method nu85ea connection pin vpdv output leave open. a25 to a0, sdrasz, sdcasz, sdwez, cke, dqm3 to dqm0 output leave open. external memory connection pins di31 to di0 input input low level. 2.2.4 pin status the following table shows the status in each operating mode of the pins that have output functions. table 2-3. pin status in each operating mode pin status pin name reset stop mode halt mode bus hold test mode vbdi31 to vbdi0 l l operating l operating vbwait l l operating l operating vbahld l l operating l operating vblast l l operating l operating vpdr15 to vpdr0 l l operating l operating nu85ea connection pins vpdv l l operating l operating ctcsi3 to ctcsi0 l retained operating l operating NT85E500 connection pins ct502i1, ct502i0 l retained operating l operating a25 to a0 undefined retained operating l operating sdrasz h h operating h operating sdcasz h h operating h operating sdwez h h operating h operating cke h l operating h operating external memory connection pins dqm3 to dqm0 h h operating h operating remark l: low-level output h: high-level output retained: retains the previous status
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 95 2.3 bus cycle function in the bus cycle function of the nt85e502, the operation settings are made using the following control registers, which are assigned to the peripheral i/o area of the nu85ea. bit units for manipulation address register name symbol r/w 1 bit 8 bits 16 bits after reset fffff4a0h sdram configuration register 0 scr0 r/w 0000h fffff4a2h sdram refresh control register 0 rfs0 r/w 0000h fffff4a4h sdram configuration register 1 scr1 r/w 0000h fffff4a6h sdram refresh control register 1 rfs1 r/w 0000h fffff4a8h sdram configuration register 2 scr2 r/w 0000h fffff4aah sdram refresh control register 2 rfs2 r/w 0000h fffff4ach sdram configuration register 3 scr3 r/w 0000h fffff4aeh sdram refresh control register 3 rfs3 r/w 0000h fffff4b0h sdram configuration register 4 scr4 r/w 0000h fffff4b2h sdram refresh control register 4 rfs4 r/w 0000h fffff4b4h sdram configuration register 5 scr5 r/w 0000h fffff4b6h sdram refresh control register 5 rfs5 r/w 0000h fffff4b8h sdram configuration register 6 scr6 r/w 0000h fffff4bah sdram refresh control register 6 rfs6 r/w 0000h fffff4bch sdram configuration register 7 scr7 r/w 0000h fffff4beh sdram refresh control register 7 rfs7 r/w 0000h
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 96 2.3.1 sdram configuration register n (scrn) this register sets the number of waits and the column address width. when more than one nt85e502 is incorporated in the system, settings can be made for each csn area (n = 7 to 0). if this register is written to, the nt85e502 will start a register write operation. this register can be read or written in 16-bit units. cautions 1. an sdram read/write cycle will not be generated prior to the execution of a register write operation. access sdram after waiting 20 clocks following execution of a program that writes to the scrn register. when setting the scrn register again after accessing sdram, first clear (to 0) the men bit of the bct0 and bct1 registers in the NT85E500 and then set (1) again (n = 7 to 0). 2. do not execute continuous write instructions to the scrn register. be sure to insert and execute another instruction between write instructions to the scrn register (n = 7 to 0). 3. when using two or more nt85e502s, do not access the sdram area until all the scrn register settings are completed (n = 7 to 0). 4. set sdram refresh control register n (rfsn) before setting the scrn register (n = 7 to 0). remarks 1. n of the register name corresponds to the csn area number. 2. the address decoder is in the NT85E500. for the addresses of each csn area, refer to the nu85e hardware user?s manual (a14874e) . figure 2-4. sdram configuration register n (scrn) (1/2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address after reset scrn 0 ltm 2 ltm 1 ltm 0 0000 bcw 1 bcw 0 sso 1 sso 0 raw 1 raw 0 saw 1 saw 0 fffff4a0h + 4n 0000h bit position bit name description set the cas latency value of a read operation. ltm2 ltm1 ltm0 cas latency 0 0 don?t care setting prohibited 0102 0113 1 don?t care don?t care setting prohibited 14 to 12 ltm2 to ltm0 remark n = 7 to 0
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 97 figure 2-4. sdram configuration register n (scrn) (2/2) bit position bit name description set the number of wait states between the bank active command and the read/write command, or between the precharge command and the bank active command. bcw1 bcw0 number of wait states 0 0 setting prohibited 011 102 113 7, 6 bcw1, bcw0 set the address shift width during on-page judgment. when the data bus size has been set to either 16 bits or 32 bits, the system does not use the lower addresses (a0 or a1 and a0). sso1 sso0 address shift width 0 0 0 bits (8-bit data bus) 0 1 1 bit (16-bit data bus) 1 0 2 bits (32-bit data bus) 1 1 setting prohibited 5, 4 sso1, sso0 set the row address width. raw1 raw0 row address width 0 0 11 bits 0 1 12 bits 1 don?t care setting prohibited 3, 2 raw1, raw0 set the column address width. saw1 saw0 column address width 0 0 8 bits 0 1 9 bits 1 0 10 bits 1 1 setting prohibited 1, 0 saw1, saw0
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 98 table 2-4. row address output address pin a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 saw1 and saw0 bits = 10 a25 to a18 a17 a16 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 saw1 and saw0 bits = 01 a25 to a18 a17 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 saw1 and saw0 bits = 00 a25 to a18 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 table 2-5. column address output (a) all bank precharge commands address pin a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 sso1 and sso0 bits = 00 a25 to a18 a17 a16 a15 a14 a13 a12 a11 1 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 sso1 and sso0 bits = 01 a25 to a18 a17 a16 a15 a14 a13 a12 1 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 sso1 and sso0 bits = 10 a25 to a18 a17 a16 a15 a14 a13 1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 (b) register write command address pin a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 sso1 and sso0 bits = 00 0 00000000000 ltm 2 ltm 1 ltm 0 0000 sso1 and sso0 bits = 01 0 0000000000 ltm 2 ltm 1 ltm 0 00000 sso1 and sso0 bits = 10 0 000000000 ltm 2 ltm 1 ltm 0 000000 (c) read/write command address pin a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 sso1 and sso0 bits = 00 a25 to a18 a17 a16 a15 a14 a13 a12 a11 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 sso1 and sso0 bits = 01 a25 to a18 a17 a16 a15 a14 a13 a12 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 sso1 and sso0 bits = 10 a25 to a18 a17 a16 a15 a14 a13 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 99 (1) address outputs and sdram connection the settings of sdram configuration register n (scrn), physical addresses, address outputs from the nt85e502, and connection of the nt85e502 and sdram for each data bus width (8 bits, 16 bits, and 32 bits) are described below. (a) 8-bit data bus a connection example of 64 mb sdram (2 mwords 8 bits 4 banks) when using an 8-bit data bus is shown below. ? scrn register settings sso1, sso0 = 00: data bus width = 8 bits raw1, raw0 = 01: row address width = 12 bits saw1, saw0 = 01: column address width = 9 bits ? physical addresses a22, a21: bank address a20 to a9: row address a8 to a0: column address ? addresses output from the nt85e502 a22, a21: bank address a11 to a0: row address (12 bits), column address (9 bits) row addresses and bank addresses output upon active command a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 bank address row address column addresses output upon read/write command a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 column address ? connection of the nt85e502 and sdram a22, a21 (nt85e502) ba0 (a13), ba1 (a12) (sdram) a11 to a0 (nt85e502) a11 to a0 (sdram)
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 100 (b) 16-bit data bus a connection example of 64 mb sdram (1 mword 16 bits 4 banks) when using a 16-bit data bus is shown below. ? scrn register settings sso1, sso0 = 01: data bus width = 16 bits raw1, raw0 = 01: row address width = 12 bits saw1, saw0 = 00: column address width = 8 bits ? physical addresses a22, a21: bank address a20 to a9: row address a8 to a1: column address ? addresses output from the nt85e502 a22, a21: bank address a12 to a1: row address (12 bits), column address (8 bits) row addresses and bank addresses output upon active command a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a25 a24 a23 a22 a21 a20 a19 a18 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 bank address row address column addresses output upon read/write command a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 column address ? connection of the nt85e502 and sdram a22, a21 (nt85e502) ba0 (a13), ba1 (a12) (sdram) a12 to a1 (nt85e502) a11 to a0 (sdram)
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 101 (c) 32-bit data bus a connection example of 128 mb sdram (64 mb sdram (1 mword 16 bits 4 banks) 2) when using a 32-bit data bus is shown below. ? scrn register settings sso1, sso0 = 10: data bus width = 32 bits raw1, raw0 = 01: row address width = 12 bits saw1, saw0 = 00: column address width = 8 bits ? physical addresses a23, a22: bank address a21 to a10: row address a9 to a2: column address ? addresses output from the nt85e502 a23, a22: bank address a13 to a2: row address (12 bits), column address (8 bits) row addresses and bank addresses output upon active command a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a25 a24 a23 a22 a21 a20 a19 a18 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 bank address row address column addresses output upon read/write command a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 column address ? connection of the nt85e502 and sdram a23, a22 (nt85e502) ba0 (a13), ba1 (a12) (sdram) a13 to a2 (nt85e502) a11 to a0 (sdram)
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 102 (2) bank address output the nt85e502 precharges the bank to be accessed at the row address output immediately after a page change as a bank precharge command. in addition, after a bank change, the nt85e502 precharges the bank accessed last at the column address output. therefore, since a bank precharge is performed either at the row address output or the column address output, always connect the pins (a22 and a21) of the nt85e502 that output bank addresses to the bank address pins (a13 and a12) of the sdram when connection is performed according to the description in 2.3.1 (1) (a) 8-bit data bus. examples of address output upon bank precharge command at a page change and a bank change when connection is performed according to the description in 2.3.1 (1) (a) 8-bit data bus are described below. (a) at a page change (8-bit data bus) since the bank to be accessed is precharged, the physical addresses (a25 to a9) to be accessed are output from the a25 to a0 pins of the nt85e502. a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a25 a24 a23 a22 a21 a20 0 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 bank address to be accessed row address (b) at a bank change (8-bit data bus) since the bank accessed last is precharged, the physical addresses (a25 to a9) accessed last are output from the a25 to a9 pins of the nt85e502. a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 bank address accessed last column address the bit that specifies the precharge mode (a10: 8-bit data bus, a11: 16-bit data bus, a12: 32-bit data bus) outputs a high level upon an all bank precharge command, and a low level during other precharges.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 103 2.3.2 sdram cycle (1) connection example figure 2-5. 64 mb sdram connection example nt85e502 sdram (1 mword 16 bits 4) a11 to a0 dq15 to dq8 clk a13, a12 cke cs ras cas ldqm hdqm we a13 to a2 a23, a22 sdrasz cke sdcasz dqm1 sdwez dqm0 dqm3 dqm2 di15 to di8 dq7 to dq0 sdram (1 mword 16 bits 4) a11 to a0 dq15 to dq8 clk a13, a12 cke cs ras cas ldqm hdqm we dq7 to dq0 NT85E500 a13 to a2 a23, a22 do7 to do0 do15 to do8 do31 to do24 do23 to do16 dc1 dc0 dc3 dc2 i/o buffer di31 to di24 di23 to di16 i/o buffer i/o buffer di7 to di0 i/o buffer sdclk csz
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 104 (2) bus timing during power-on or refresh, an all bank precharge command is always issued to the sdram. therefore, when the sdram is accessed after this, the active command and read/write command are issued in order (<1> in figure 2-6 ). when a page change occurs, the precharge command, active command, and read/write command are issued in order (<2> in figure 2-6 ). when a bank change occurs, the active command and read/write command for the bank to be accessed next are issued in order. immediately after the read/write command, the precharge command for the bank that was accessed immediately before the currently accessed bank is issued (<3> in figure 2-6 ). figure 2-6. state transition of sdram access <1> on-page access bank change page change bank a precharge command bank change <3> <2> all bank precharge command (power-on, refresh) bank a active command read/write command read/write command bank a precharge command bank a active command bank a read/write command bank b active command bank b read/write command bank a active command bank a read/write command
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 105 the write data to the sdram is output from the NT85E500, and the read data from the sdram is input to the nt85e502. figure 2-7. read/write data flow for sdram remark when the addresses (a25 to a0) are output from the nt85e502 to the sdram, a25 to a0 output from the NT85E500 becomes low level. sdram asic nu85ea NT85E500 vma25 to vma0 vba25 to vba0 a25 to a0 dc3 to dc0 a25 to a0 nt85e502 vbdi31 to vbdi0 vba25 to vba0 a25 to a0 di31 to di0 output buffer vbdo31 to vbdo0 d31 to d0 i/o buffer flow of write data do31 to do0 vbdo31 to vbdo0 flow of read data vbdi31 to vbdi0
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 106 examples of the bus timing for an sdram read or write are shown below. an sdram bus cycle consists of the following states. ? allpre state: all bank precharge command state. ? refw state: refresh wait state. ? regw state: register write command state. ? tact state: bank active command state. ? tbcw state: wait state that is inserted when bcw is set to 2 or 3. ? ti state idle state that is inserted according to the setting of the bcc register (inserted only during a read operation). ? tlate state: latency-amount wait state. ? tprec state: bank precharge command state. ? tread state: read command state. ? tref state: refresh command state. ? trpw state: wait state between the read/write cycles following a register write operation. ? tw state: wait state. ? tw0 state: wait state indicating the status of waiting prior to the start of a register write operation. ? twe state: state indicating the end of the write cycle. ? twpre state: state indicating precharge. precharges the bank accessed last only when the bank changes. ? twr state: write command state. remarks 1. circles indicate sampling timing. 2. : unknown state (output) or any level (input). 3. for details of vsb signals (vbxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) . 4. bcw: wait state set by the bcw1 and bcw0 bits of the scrn register (n = 7 to 0) 5. the address/bank address output upon a bank precharge command is the address/bank address accessed last.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 107 remark refresh interval 1/2: half period of the refresh interval set by the rfsn register (n = 7 to 0) figure 2-8. sdram register write operation timing note NT85E500 signal refresh (1st time) end refresh (8th time) end vba25 to vba0 (input) vbclk (input) sdclk (output) note vbstz (input) note tw0 tw0 tw0 vareq (output) note vaack (input) note (input) note cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) do31 to do0 (output) note h vdcsz (input) vbwrite (input) vpstb (input) tw0 tw0 allpre refw refw refw tref refw refw refw refw tref refw refw refw regw trpw trpw trpw trpw trpw valid refresh command (2nd time) refresh 7 register write command sdram access enable refresh interval 1/2 tw0 tw0 tw0 refresh command (1st time) h between cpu core and memc between memc and sdram scrn register write a25, a24, a21 to a13 all bank precharge command vbdo31 to vbdo0
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 108 (b) off-page, bank change, cas latency = 3, bcw = 2, idle state = 2 figure 2-9. sdram single read cycle (32-bit data bus, word access) (1/2) (a) off-page, bank change, cas latency = 2, bcw = 1 note NT85E500 signal sdram read cycle vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdi31 to vbdi0 (output) vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh h read command fh 0h do31 to do0 (output) note bfh tw tread tlate tlate 0h adr. col. fh tact adr. adr. bank row adr. row bank active command between cpu core and memc between memc and sdram (0,0,1) (0,0,0) bcw bank precharge command adr. adr. adr. bank adr. vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdi31 to vbdi0 (output) vdcsz (input) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh h read command fh do31 to do0 (output) note bfh tw tread tlate tlate 0h col. fh tact adr. adr. bank row bank active command tbcw tlate ti ti 0h bcw adr. row sdram read cycle between cpu core and memc between memc and sdram vbwait (output) (0,0,1) (0,0,0) bank precharge command adr. bank adr. adr. adr. adr.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 109 (d) on-page, cas latency = 2 figure 2-9. sdram single read cycle (32-bit data bus, word access) (2/2) (c) off-page, page change note NT85E500 signal vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdi31 to vbdi0 (output) vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh sdram read cycle h fh 0h d31 to d0 (i/o) note tw tread tlate tlate col. tact adr. adr. adr. tprec bank row bfh fh read command bank active command bank precharge command bank adr. between cpu core and memc between memc and sdram (0,0,1) 0h (0,0,0) adr. row vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdi31 to vbdi0 (output) vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh h read command fh 0h do31 to do0 (output) note tw tread tlate tlate h h fh between cpu core and memc between memc and sdram sdram read cycle (0,0,1) 0h (0,0,0) adr. adr. bfh col.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 110 (b) off-page, page change figure 2-10. sdram single write cycle (32-bit data bus, word access) (1/2) (a) off-page, bank change note NT85E500 signal vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdo31 to vbdo0 (input) note vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh sdram write cycle h adr. row adr. col. adr. fh 0h fh do31 to do0 (output) note tw tact twr twpre twe (0,0,1) (0,0,0) tprec 0h adr. bank row bfh write command bank active command bank precharge command adr. between cpu core and memc between memc and sdram vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdo31 to vbdo0 (input) note vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh sdram write cycle h write command adr. row adr. row col. adr. bank adr. fh 0h fh do31 to do0 (output) note tw tact twr twpre twe bfh bank active command adr. between cpu core and memc between memc and sdram (0,0,1) 0h (0,0,0) bank precharge command adr. adr. bank adr.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 111 figure 2-10. sdram single write cycle (32-bit data bus, word access) (2/2) (c) on-page note NT85E500 signal vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdo31 to vbdo0 (input) note vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh sdram write cycle h write command adr. col. 0h fh do31 to do0 (output) note h fh (0,0,1) (0,0,0) 0h bfh tw twr twpre twe adr. between cpu core and memc between memc and sdram
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 112 figure 2-11. sdram continuous read cycle (32-bit data bus, word access, on-page) note NT85E500 signal vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdi31 to vbdi0 (output) vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh sdram read cycle h read command fh 0h do31 to do0 (output) note tw tread tlate tlate h h fh sdram read cycle tw tread tlate tlate fh 0h read command sdram read cycle tw tread tlate tlate fh 0h read command sdram read cycle tw tread tlate tlate fh 0h read command between cpu core and memc between memc and sdram bfh adr. col. adr. adr. adr. adr. bfh col. bfh col. bfh col. adr. adr. adr. (0,0,1) (0,0,0) 0h
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 113 figure 2-12. sdram continuous write cycle (32-bit data bus, word access, on-page) note NT85E500 signal vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdo31 to vbdo0 (input) note vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note (0,0,1) 0h (0,0,0) fh sdram write cycle h write command sdram write cycle sdram write cycle sdram write cycle write command write command write command h fh 0h 0h fh 0h fh 0h fh fh bfh l tw twr twpre twe tw twr twpre twe tw twr twpre twe tw twr twpre twe do31 to do0 (output) note between cpu core and memc between memc and sdram col. col. col. col. adr. adr. adr. adr. adr. adr. adr. adr.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 114 figure 2-13. sdram sequential read cycle (16-bit data bus, word access, page change, cas latency = 2, bcw = 2) note NT85E500 signal vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdi31 to vbdi0 (output) vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a12 (output) a23, a22 (output) a11 (output) a10 to a1 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh sdram read cycle h bank a read command fh do31 to do0 (output) note (0,0,1) tw tread tread tlate fh tact adr. adr. bank row adr. row tbcw tlate 0h (0,0,0) adr. adr. adr. bank bank adr. adr. adr. row col. col. adr. row tprec tact tbcw bcw tread tbcw tread tlate tlate sdram read cycle ch (0,0,0) (0,0,1) adr. adr. col. col. bfh 0h fh bank a read command (on-page) bank a active command bank a precharge command bank a active command bank a read command bank a read command (on-page) tw between cpu core and memc between memc and sdram (0,0,1) bcw bcw adr. adr. adr. adr.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 115 figure 2-14. sdram sequential read cycle (8-bit data bus, word access, page change, cas latency = 2, bcw = 2) note NT85E500 signal vba25 to vba0 (i nput) vbwrite (input) (input) vbstz (input) note (input) vbdi31 to vbdi0 (output) vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) (output) a23, a22 (output) a10 (output) a9 to a0 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) (input) note vbclk (input) sdclk (output) note fh sdram read cycle h bank a read command fh do31 to do0 (output) note tw tread tread tlate tact adr. adr. bank row adr. row tbcw tlate col. eh bfh tread tread col. col. fh adr. bank bank adr. adr. adr. row adr. row tprec tact tbcw tread tbcw tread tlate tlate sdram read cycle col. fh tread tread col. col. tw tread tread tread tread tlate tlate sdram read cycle col. col. col. bank a read command bank a read command bank a read command bank a active command bank a precharge command bank a active command tw fh 0h between cpu core and memc between memc and sdram 0h 0h col. col. col. (0,0,1) (0,1,0) (0,0,1) (0,0,0) (0,1,0) (0,0,1) (0,0,0) (0,0,1) (0,0,0) (0,1,0) bcw bcw bcw vbctyp2 to vbctyp0 vbbenz3 to vbbenz0 vbseq2 to vbseq0 a25, a24, a21 to a11 adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. adr. bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 116 figure 2-15. sdram sequential write cycle (16-bit data bus, word access, bank change, cas latency = 2, bcw = 1) note NT85E500 signal vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdo31 to vbdo0 (input) note vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a12 (output) a23, a22 (output) a11 (output) a10 to a1 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh h adr. row adr. row col. adr. bank fh do31 to do0 (output) note tw tact twr twpre twe ch (0,0,1) bfh bank a active command twr bcw (0,0,0) adr. col. ch bank a write command bank a write command adr. row adr. row col. adr. bank tw tact twr twpre twe (0,0,1) twr bcw (0,0,0) adr. col. ch bank b write command bank b write command fh col. adr. tw twr twpre twe twr (0,0,0) adr. ch bank b write command adr. bank col. fh bank a precharge command bank b active command bank b write command between cpu core and memc between memc and sdram tw (0,0,1) adr. fh (0,0,1) adr. adr. adr. adr. adr. adr. sdram write cycle sdram write cycle sdram write cycle
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 117 figure 2-16. sdram sequential write cycle (8-bit data bus, word access, bank change, cas latency = 2, bcw = 1) note NT85E500 signal vba25 to vba0 (input) vbwrite (input) vbbenz3 to vbbenz0 (input) vbstz (input) note vbseq2 to vbseq0 (input) vbdo31 to vbdo0 (input) vdcsz (input) vbwait (output) vbahld (output) vblast (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a11 (output) a23, a22 (output) a10 (output) a9 to a0 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) vbctyp2 to vbctyp0 (input) note vbclk (input) sdclk (output) note fh sdram write cycle h adr. row adr. row col. adr. bank fh do31 to do0 (output) note tw tact twr (0,1,0) bank a active command twr bcw col. eh bank a wri te command bank a wri te command twpre twe sdram write cycle adr. row adr. row col. adr. bank tw tact twr twpre twe (0,1,0) twr bcw adr. col. eh bank b wri te command bank b wri te command fh fh bank a precharge command bank b active command twr twr (0,0,0) (0,0,1) adr. adr. adr. adr. adr. col. col. bank a wri te command bank a wri te command twr twr (0,0,1) (0,0,1) (0,0,0) bank adr. col. col. eh bfh bank b wri te command bank b wri te command between cpu core and memc between memc and sdram adr. adr. adr. adr. adr. adr. adr. adr. adr. adr.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 118 2.3.3 sdram refresh control register n (rfsn) it is possible to generate an sdram cbr refresh cycle and a self-refresh cycle in the nt85e502. refresh enable and the refresh interval are set by this register. when more than one nt85e502 is incorporated in the system, settings can be made for each csn area (n = 7 to 0). this register can be read or written in 16-bit units. remarks 1. n of the register name corresponds to the csn area number. 2. the address decoder is in the NT85E500. for the addresses of each csn area, refer to the nu85e hardware user?s manual (a14874e) . figure 2-17. sdram refresh control register n (rfsn) (1/2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address after reset rfsn ren 0 0 0 0 0 rcc 1 rcc 0 00 rin 5 rin 4 rin 3 rin 2 rin 1 rin 0 fffff4a2h + 4n 0000h bit position bit name description sets refresh enable. ren refresh setting 0 refresh disabled 1 refresh enabled 15 ren set the source clock factor for the refresh interval counter. rcc1 rcc0 count source clock factor (cfac) 0032 0 1 128 1 0 256 1 1 setting prohibited 9, 8 rcc1, rcc0 remark refresh count clock (trcy) = cfac/ : internal system clock (vbclk) remark n = 7 to 0
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 119 figure 2-17. sdram refresh control register n (rfsn) (2/2) bit position bit name description set the refresh interval factor. rin5 rin4 rin3 rin2 rin1 rin0 interval factor (ifac) 0000001 0000012 0000103 0000114 ::::::: 11111164 5 to 0 rin5 to rin0 caution to change the settings of the rfsn register, follow the procedure below (n = 7 to 0). <1> clear (0) the ren bit. <2> set the new values to the rcc1, rcc0 and rin5 to rin0 bits and set (1) the ren bit. in addition, when changing the refresh interval, set a value that allows a refresh to be performed in time during the interval change. table 2-6. examples of sdram refresh intervals interval factor (ifac) note refresh interval prescribed value ( s) refresh count clock (trcy) when = 20 mhz when = 33 mhz when = 50 mhz when = 66 mhz 32/ 9 (14.4) 16 (15.5) 24 (15.4) 32 (15.5) 128/ 2 (12.8) 4 (15.5) 6 (15.4) 8 (15.5) 15.6 256/ 1 (12.8) 2 (15.5) 3 (15.4) 4 (15.5) note values in parentheses indicate the calculated refresh interval values ( s). refresh interval ( s) = trcy ifac remark : internal system clock (vbclk)
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 120 2.3.4 cbr refresh function the nt85e502 activates a cbr refresh cycle for every refresh interval set to the rfsn register (n = 7 to 0). (1) cbr refresh flow <1> when a refresh request is generated from the settings of the rfsn register, a cbr refresh request is sent to the NT85E500 from the nt85e502. <2> the NT85E500 outputs the vsb mastership request signal (vareq) to the nu85ea. <3> an acknowledge signal (vaack) for the vareq signal is returned from the nu85ea to the NT85E500. <4> when the vaack signal is received, the NT85E500 activates the refrqz signal from the rising edge of the vbclk signal, and starts a cbr refresh. (2) cbr refresh timing an example of cbr refresh timing is shown below. remarks 1. for details of vsb signals (vbxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) . 2. : unknown state (output) or any level (input). 3. bcw 4clk: the number of wait states set by the bcw1 and bcw0 bits of the scrn register a 4-clock wait are inserted (n = 7 to 0).
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 121 figure 2-18. sdram cbr refresh timing note NT85E500 signal vba25 to vba0 (input) vbclk (input) sdclk (output) note trpw trpw trpw trpw allpre refw refw refw tref refw vbdi31 to vbdi0 (output) vdcsz (input) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) all bank precharge command vareq (output) note vaack (input) note trpw h h refresh command bcw 4clk refw refw refw trpw trpw trpw trpw trpw between cpu core and memc between memc and sdram refrqz (output) note
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 122 2.3.5 self-refresh function if either the nu85ea undergoes a transition to stop mode, or the selfref signal of the NT85E500 becomes active, the NT85E500 becomes the vsb bus master and the external sdram self-refresh cycle is started. (1) self-refresh flow <1> either a stop mode request signal (stprq) is input to the NT85E500 from the nu85ea, or a self- refresh request signal (selfref) is input to the NT85E500 from outside the NT85E500. <2> the NT85E500 outputs a vsb mastership request signal (vareq) to the nu85ea. <3> the nu85ea returns an acknowledge signal for the vareq signal (vaack) to the NT85E500. <4> after receiving the vaack signal, the NT85E500 activates the refrqz signal from the rising edge of the next vbclk signal, and starts a self-refresh. <5> transition into the self-refresh status in the entire sdram is completed. <6> the NT85E500 returns an acknowledge signal for the stprq signal (stpak) to the nu85ea. <7> the stprq signal becomes inactive. <8> suspension of self-refresh begins. <9> suspension of self-refresh in the entire sdram is completed. <10> the vareq signal becomes inactive. <11> normal status resumes. (2) self-refresh timing an example of self-refresh timing is shown below. remarks 1. for details of vsb signals (vbxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) . 2. : unknown state (output) or any level (input). 3. bcw 4clk: the number of wait states set by the bcw1 and bcw0 bits of the scrn register a 4-clock wait are inserted (n = 7 to 0).
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 123 figure 2-19. sdram self-refresh timing note NT85E500 signal vbclk (input) sdclk (output) note vbdi31 to vbdi0 (output) cke (output) csz7 to csz0 (output) note dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) di31 to di0 (input) all bank precharge command vareq (output) note vaack (input) note h nop command vdcsz (input) stprq (input) note stpak (output) note refresh command bcw 4clk trpw trpw trpw trpw allpre refw refw refw tref refw refw trpw refw refw refw trpw refw trpw trpw trpw trpw trpw between cpu core and memc between memc and sdram refrqz (output) note self-refresh mode nop command
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 124 2.3.6 notes on refresh function the sdram refresh is not always performed in the interval set by the rfsn register. if a refresh request is generated in the case below, the bus cycle ends and the refresh request is held pending until the NT85E500 secures bus mastership. (1) when the nu85ea operates as the bus master and the vsb bus cycle is generated the following cases: ? while memory instruction fetch and data access (including npb access) are being performed from the nu85ea via the vsb. ? during dma transfer using the vsb (held pending until the current dma transfer ends in the case of single transfer, single-step transfer, and block transfer. in line transfer, held pending until the one line (four transfers) ends (see figure 2-20 )). ? during instruction cache and data cache refill (held pending until one-line refill (four words) ends when a miss-hit has been generated and one-line refill is performed from memory to the vsb. in the case of an instruction auto-fill, held pending until the one-line (four words) refill ends (since the vmlock signal of the nu85ea becomes inactive, bus can be released every one line, so the refresh request can be acknowledged)). (2) in a bus hold state set by an external bus master if a bus hold request and a refresh request conflict, the bus hold request takes precedence. when a refresh request is generated during a bus hold, the refrqz signal of the NT85E500 becomes active and refresh request generation notification can be sent to the external bus master. to shift to the refresh cycle, cancel the bus hold request using this signal. if no external devices can be the bus master and the hldrqz pin is fixed to high-level input, the bus hold request is not generated. so, in that case, it is not necessary to consider conflict with a bus hold.
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 125 figure 2-20. refresh timing during dma line transfer notes 1. nu85ea signal 2. NT85E500 signal 3. ored signals of the NT85E500 and nt85e502. ffh 3h 2h 0h vmttyp1, vmttyp0 (output) note 1 vba25 to vba0 (input) vbwrite (input) vbstz (input) note 2 vbwait (output) note 2 vbdi31 to vbdi0 (output) vbbenz3 to vbbenz0 (input) vbctyp2 to vbctyp0 (input) note 2 vmsize1, vmsize0 (output) note 1 vdcsz7 to vdcsz0 (input) note 2 di31 to di0 (input) note 2 rdz (output) note 2 a25 to a0 (output) note 3 vbseq2 to vbseq0 (input) vbclk (input) vbdc (output) note 1 dmarqn (input) note 1 dmactvn (output) note 1 wrz3 to wrz0 (output) note 2 csz7 to csz0 (output) note 2 vmlock (output) note 1 3h 0h 2h 0h 6h fdh sdcasz (output) sdwez (output) vbdo31 to vbdo0 (input) note 2 do31 to do0 (output) note 2 vbdv (output) note 1 ctcsi1 (output) sdrasz (output) vareq (input) note 1 vaack (output) note 1 refrqz (output) note 2 3h 2h 0h 3h 2h 3h 2h 0h 3h 2h 0h 3h 2h 0h 3h 2h 0h 2h 6h 6h 6h 6h 6h 6h 6h 6h 0h 0h 0h 0h 0h 0h 0h 0h 0h 1h 1h 1h 1h 1h 1h 1h 1h 1h ch ch 3h 3h ch ch 3h 3h ch fh fh fh fh fh fh fh fh fdh ffh ffh fdh fdh ffh ffh fdh fdh ffh ffh fdh fdh ffh fdh fh fh 3h fh ch fh ch 3h fh ffh fdh fdh ffh ffh fdh fdh ffh ffh fdh fdh ffh ffh fdh fdh fdh ffh fbh fbh ffh ffh refresh request refresh cycle
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 126 2.4 test function the nt85e502 can be tested using the nu85ea test mode. to test the nt85e502, connect it to the nu85ea as follows (the nt85e502 is connected to the cs7 and cs3 areas). figure 2-21. connection of nt85e502 to nu85ea in test mode remark for details about test modes, refer to the nu85e hardware user?s manual (a14874e) . vsb NT85E500 phtdin0 phtdin1 phtdo0 phtest phtdin1 phtdin0 phtdo0 phtest tbi39 tbi0 ? ? tbo34 tbo0 ? test bunri ? vbclk vbclk vptclk vpresz nt85e502 vptclk vpresz nt85e502 vptclk vpresz nu85ea vptclk vpresz phtdo1 phtdo1 mten ctlo1 ctlo0 ctcso4 to ctcso0 ctcsi3 to ctcsi0 ct502o1, ct502o0 ct502i1, ct502i0 mten ctlo1 ctlo0 ctcso4 to ctcso0 ctcsi3 to ctcsi0 ct502o1, ct502o0 ct502i1, ct502i0 mten ctlo1 ctlo0 ctcso74 to ctcso70 ctcsi73 to ctcsi70 ct502o71, ct502o70 ct502i71, ct502i70 ctcso34 to ctcso30 ctcsi33 to ctcsi30 ct502o31, ct502o30 ct502i31, ct502i30
chapter 2 nt85e502 preliminary user's manual a15019ej3v0um 127 2.4.1 pin processing when in test mode (1) external memory connection pins these operate the same in test mode as in normal mode. refer to 2.2.4 pin status regarding the pin status. input pins (di31 to di0) are ignored regardless of the values that are input. (2) test mode pins connect test mode pins to the nu85ea as shown in figure 2-21. (3) other pins make other pins the same as in normal mode. refer to 2.2.4 pin status regarding the pin status.
preliminary user's manual a15019ej3v0um 128 appendix a connection example an example of the connection of the nu85ea, memcs (NT85E500 and nt85e502), and external memories (sram and sdram) is shown below.
appendix a connection example preliminary user's manual a15019ej3v0um 129 notes 4. used for self-refresh request 5. used when memory with a byte enable control function is connected 6. used for initial value settings figure a-1. connection example of nu85ea, memcs and external memories (sram and sdram) notes 1. used for dma flyby transfer 2. used for bus hold cycle 3. used for external wait control memc (nt85e502) vdcsz vbbenz3 to vbbenz0 vpresz vbwait vbahld vbclk vba25 to vba0 vblast vpstb vpwrite vpdw15 to vpdw0 vptclk vbwrite mten ctlo1, ctlo0 ct502ox1, ct502ox0 ct502ix1, ct502ix0 ctcsox4 to ctcsox0 ctcsix3 to ctcsix0 vbseq2 to vbseq0 a25 to a0 a25 to a0 d31 to d0 cs di31 to di0 sdrasz sdcasz sdwez cke dqm3 to dqm0 sdram a25 to a0 d31 to d0 sdrasz sdcasz sdwez cke dqm3 to dqm0 oe we note 3 note 1 nu85ea vdcsz7 to vdcsz0 vmbenz3 to vmbenz0 vmctyp2 to vmctyp0 vbdo31 to vbdo0 vpresz vmstz vmwait vmahld vma25 to vma0 vmlast vmseq2 to vmseq0 vareq vaack stprq stpak vpubenz vpa13 to vpa0 vpstb vpwrite vpdi15 to vpdi0 phtest phtdo1, phtdo0 phtdin1, phtdin0 vptclk vmwrite memc (NT85E500) vdcsz7 to vdcsz0 vbbenz3 to vbbenz0 vbctyp2 to vbctyp0 vbdi31 to vbdi0 vpresz vbstz vbwait vbahld vbclk vba25 to vba0 vblast vbseq2 to vbseq0 vareq vaack stprq stpak vpubenz vpa13 to vpa0 vpstb vpwrite vpdr15 to vpdr0 phtest phtdo1, phtdo0 phtdin1, phtdin0 vptclk vbwrite mten ctlo1, ctlo0 ct502ox1, ct502ox0 ct502ix1, ct502ix0 ctcsox4 to ctcsox0 ctcsix3 to ctcsix0 a25 to a0 di31 to di0 dc3 to dc0 iordz iowrz csz0 hldrqz hldakz waitz rdz wrz3 to wrz0 vbclk vbclk sdclk asic cs0 cs3 cs sdclk note 2 hldakz vbdo31 to vbdo0 vpdw15 to vpdw0 vbdi31 to vbdi0 vpdo15 to vpdo0 vbdi31 to vbdi0 vpdr15 to vpdr0 do31 to do0 selfref benz3 to benz0 i/o buffer csz3 note 4 note 5 sram mce bcpen mpxen note 6
preliminary user's manual a15019ej3v0um 130 appendix b index [a] a25 to a0? ....................................................... 28, 93 acn1, acn0............................................................. 39 address setting wait control register ....................... 39 asc ......................................................................... 39 astbz ..................................................................... 33 [b] bcc ......................................................................... 40 bcn1, bcn0............................................................. 40 bcp ................................................................... 33, 63 bcpen .................................................................... 28 bct0, bct1 ............................................................ 37 bcw1, bcw0.......................................................... 97 bcystz .................................................................. 31 benz3 to benz0 .................................................... 31 block diagram (NT85E500) ..................................... 17 block diagram (nt85e502) ..................................... 85 btn1, btn0 ............................................................. 38 bus arbitration controller ......................................... 18 bus cycle control register ........................................ 40 bus cycle function (NT85E500) ............................... 37 bus cycle function (nt85e502) ............................... 95 bus cycle period control register ............................. 63 bus cycle type configuration registers 0 and 1........ 37 bus hold function..................................................... 61 busst..................................................................... 31 [c] cke ......................................................................... 93 configuration example (NT85E500) ........................ 19 configuration example (nt85e502) ........................ 86 csz7 to csz0 ......................................................... 30 ct501in2 to ct501in0 ............................................ 33 ct501on3 to ct501on0 ........................................ 33 ct502i1, ct502i0 ................................................... 92 ct502in0................................................................. 33 ct502in1................................................................. 32 ct502o1, ct502o0 ............................................... 92 ct502on0 ............................................................... 33 ct502on1 ............................................................... 33 ctcsi3 to ctcsi0 .................................................. 92 ctcsin0.................................................................. 32 ctcsin1.................................................................. 32 ctcsin2.................................................................. 32 ctcsin3.................................................................. 32 ctcso4 to ctcso0.............................................92 ctcson0 ..............................................................32 ctcson1 ..............................................................32 ctcson2 ..............................................................32 ctcson3 ..............................................................32 ctcson4 ..............................................................32 ctl501 ..................................................................33 ctlo1, ctlo0................................................32, 92 [d] data flow................................................................67 data flow for byte access (8 bits)...........................68 data flow for halfword access (16 bits)..................72 data flow for word access (32 bits)........................76 data wait control registers 0 and 1 ........................41 dc3 to dc0 ...........................................................29 di31 to di0.......................................................28, 93 do31 to do0 .........................................................28 dqm3 to dqm0 .....................................................93 dstbz ...................................................................33 dwc0, dwc1........................................................41 dwn2 to dwn0......................................................41 [h] hldakz...........................................................29, 93 hldrqz ................................................................29 [i] iordz....................................................................28 iowrz...................................................................28 [l] ltm2 to ltm0 .......................................................96 list of pin functions (NT85E500) ...........................21 list of pin functions (nt85e502) ...........................89 [m] ma6 to ma3 ...........................................................52 mce.......................................................................28 men .......................................................................38 mpxcz ..................................................................33 mpxen ..................................................................33 mten...............................................................32, 93 [n] NT85E500..............................................................14
appendix b index preliminary user's manual a15019ej3v0um 131 nt85e502 ............................................................... 82 nt85e502 interface block....................................... 18 [p] page rom configuration register ............................ 51 page rom controller............................................... 15 page rom cycle ..................................................... 53 phtdin1, phtdin0................................................ 33 phtdo1, phtdo0 ................................................. 33 phtest .................................................................. 33 pin status (NT85E500) ............................................ 35 pin status (nt85e502) ............................................ 94 pin processing when in test mode (nt85e502) .... 127 pisl ........................................................................ 33 prc......................................................................... 51 prw2 to prw0....................................................... 51 [r] raw1, raw0.......................................................... 97 rcc1, rcc0......................................................... 118 rdcyz .................................................................... 33 rdz ......................................................................... 28 recommended connection of unused pins (NT85E500)............................................................. 34 recommended connection of unused pins (nt85e502)............................................................. 94 refrqz.................................................................. 31 register block ......................................................... 18 ren....................................................................... 118 rfsn ..................................................................... 118 rin5 to rin0 ......................................................... 119 rwc7 to rwc0 ...................................................... 33 [s] saw1, saw0 .......................................................... 97 scrn....................................................................... 96 sdcasz.................................................................. 93 sdclk .................................................................... 31 sdram configuration register n.............................. 96 sdram cycle ........................................................ 103 sdram refresh control register n ......................... 118 sdrasz.................................................................. 93 sdwez ................................................................... 93 self-refresh function .............................................. 122 selfref ................................................................ 31 sram-and-i/o controller ......................................... 15 sram cycle............................................................. 43 sram/page rom controller.................................... 18 sso1, sso0 ......................................................... 97 stop function ....................................................... 65 stpak................................................................... 27 stprq .................................................................. 27 symbol diagram (NT85E500) ................................ 16 symbol diagram (nt85e502) ................................ 84 [t] test bus interface block ........................................ 18 test function (NT85E500) ..................................... 66 test function (nt85e502) ................................... 126 [v] vaack .................................................................. 26 vareq .................................................................. 26 vba25 to vba0 ............................................... 24, 90 vbahld .......................................................... 26, 91 vbbenz3 to vbbenz0 ................................... 24, 90 vbclk............................................................. 24, 90 vbctyp2 to vbctyp0 ......................................... 24 vbdi31 to vbdi0............................................. 25, 90 vbdo31 to vbdo0 ............................................... 25 vblast........................................................... 26, 91 vbseq2 to vbseq0 ....................................... 25, 90 vbstz ................................................................... 26 vbwait........................................................... 26, 91 vbwrite ........................................................ 26, 91 vdcsz .................................................................. 90 vdcsz7 to vdcsz0 ............................................. 24 vpa13 to vpa0 ..................................................... 27 vpdr15 to vpdr0.......................................... 27, 92 vpdv............................................................... 27, 92 vpdw15 to vpdw0 ........................................ 27, 92 vpresz ......................................................... 27, 92 vpstb............................................................. 27, 92 vptclk........................................................... 33, 93 vpubenz.............................................................. 27 vpwrite ........................................................ 27, 92 [w] waitz ................................................................... 29 wrz3 to wrz0 ..................................................... 28
preliminary user's manual a15019ej3v0um 132 appendix c revision history a history of the revisions up to this edition is shown below. the page in the ?page? column indicates the page in the previous edition. (1) 1st 2nd edition (1/2) page contents p.16 addition of note to 1.1.1 (1) sram-and-i/o controller p.16 modification of 1.1.1 (2) page rom controller p.19 modification of 1.1.3 (c) bus arbitration controller p.27 modification of 1.2.2 (1) (n) vbahld p.27 modification of 1.2.2 (1) (o) vblast p.28 modification of 1.2.2 (1) (v) vpdv p.33 modification of 1.2.3 recommended connection of unused pins p.34 modification of table 1-4 pin status in each operating mode p.37 modification of caution in figure 1-3 bus cycle type configuration registers 0 and 1 (bct0 and bct1) p.41 addition of description to 1.3.4 (1) external wait function p.41 addition of description and figure to 1.3.4 (2) data wait control registers and external waits p.45 modification of figure 1-9 sram write timing p.56 modification of figure 1-17 page rom read timing p.58 modification of 1.3.8 (1) bus hold procedure p.58 modification of 1.3.8 (2) bus hold release procedure p.60 addition of caution to 1.3.9 bus cycle period control register (bcp) p.80 addition of remark to 2.1 outline p.81 modification of 2.1.1 features p.89 modification of 2.2.2 (1) (i) vbahld p.90 modification of 2.2.2 (1) (j) vblast p.90 modification of 2.2.2 (1) (m) vpdv p.91 modification of 2.2.2 (3) (g) dqm3 to dqm0 p.92 modification of table 2-3 pin status in each operating mode p.94 modification of caution 1 in 2.3.1 sdram configuration register n (scrn) p.95 modification of figure 2-4 sdram configuration register n (scrn) pp.97 to 100 addition of (1) address output and sdram connection and (2) bank address output to 2.3.1 sdram configuration register n (scrn) p.101 modification of figure 2-5 64 mb sdram connection example p.104 addition of remark 5 to 2.3.2 (2) bus timing p.106 modification of figure 2-9 sdram single read cycle (32-bit data bus, word access) pp.108, 109 modification of figure 2-10 sdram single write cycle (32-bit data bus, word access) p.114 modification of figure 2-15 sdram sequential write cycle (16-bit data bus, word access, bank change, cas latency = 2, bcw = 1)
appendix c revision history preliminary user's manual a15019ej3v0um 133 (2/2) page contents p.115 modification of figure 2-16 sdram sequential write cycle (8-bit data bus, word access, bank change, cas latency = 2, bcw = 1) p.117 modification of figure 2-17 sdram refresh control register n (rfsn) p.118 addition of 2.3.4 cbr refresh function p.119 modification of figure 2-18 sdram cbr refresh timing p.120 modification of 2.3.5 (1) self-refresh flow p.121 modification of figure 2-19 sdram self-refresh timing p.122 addition of 2.3.6 notes on refresh function p.123 addition of figure 2-20 refresh timing during dma line transfer p.124 modification of figure 2-21 connection of nt85e502 to nu85e in test mode
preliminary user's manual a15019ej3v0um 134 [memo]
although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: +82-2-528-4411 p.r. china nec electronics shanghai, ltd. nec electronics taiwan ltd. fax: +86-21-6841-1137 address north america nec electronics inc. corporate communications dept. fax: +1-800-729-9288 +1-408-588-6130 europe nec electronics (europe) gmbh market communication dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 taiwan asian nations except philippines nec electronics singapore pte. ltd. fax: +886-2-2719-5951 fax: +65-250-3583 japan nec semiconductor technical hotline fax: +81- 44-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 02.3 name company from: tel. fax facsimile message

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